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5.3.3.1 CONDITION CODE REGISTER. The CCR portion of the SR contains five bits that
indicate the result of a processor operation. Table 5-3 lists the effect of each instruction on
these bits. The carry bit and the multiprecision extend bit are separate in the M68000
Family to simplify programming techniques that use them. Refer to Table 5-7 as an
example.
Operations
ABCD
ADD, ADDI, ADDQ
ADDX
AND, ANDI, EOR, EORI,
MOVEQ, MOVE, OR,
ORI, CLR, EXT, NOT,
TAS, TST
CHK
CHK2, CMP2
SUB, SUBI, SUBQ
SUBX
CMP, CMPI, CMPM
DIVS, DIVU
MULS, MULU
SBCD, NBCD
NEG
NEGX
ASL
ASL (r = 0)
LSL, ROXL
LSR (r = 0)
ROXL (r = 0)
ROL
ROL (r = 0)
ASR, LSR, ROXR
ASR, LSR (r = 0)
ROXR (r = 0)
5-20
Freescale Semiconductor, Inc.
Table 5-3. Condition Code Computations
X
N
Z
V
*
U
?
U
*
*
*
?
*
*
?
?
—
*
*
0
—
*
U
U
—
U
?
U
*
*
*
?
*
*
?
?
—
*
*
?
—
*
*
?
—
*
*
?
*
U
?
U
*
*
*
?
*
*
?
?
*
*
*
?
—
*
*
0
*
*
*
0
—
*
*
0
—
*
*
0
—
*
*
0
—
*
*
0
*
*
*
0
—
*
*
0
—
*
*
0
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
C
Special Definition
?
C = Decimal Carry
R
R0
Z = Z
?
V = Sm
Dm
R V S
C = Sm
Dm V R
Dm V Sm
R V S
?
V = Sm
Dm
Dm V R
C = Sm
Dm V Sm
R
R0
Z = Z
0
U
?
Z = (R = LB) V R = UB
C = (LB < UB)
(IR < LB) V R > UB) V
UB < LB)
(R > UB)
V = S
R V Sm
?
Dm
C = Sm
D V Rm
D V Sm
?
V = S
Dm
R V Sm
C = Sm
D V Rm
D V Sm
R
R0
Z = Z
V = S
R V Sm
?
Dm
C = Sm
D V Rm
D V Sm
0
V = Division Overflow
0
V = Multiplication Overflow
?
C = Decimal Borrow
R
R0
Z = Z
?
V = Dm
Rm
C = Dm V Rm
?
V = Dm
Rm
C = Dm V Rm
R
R0
Z = Z
?
V = Dm
( D – 1 V
(Dm–1 V
+ Dm – r)
C = D – r + 1
0
?
C = Dm – r + 1
0
?
C = X
?
C = Dm – r + 1
0
?
C = Dr – 1
0
?
C = X
D
Rm
R
D
Rm
R
(R < LB)
D
Rm
Rm
D
Rm
Rm
D
Rm
Rm
V D – r ) V D
MOTOROLA
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