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Table 5-2. Instruction Set Summary (Concluded)
Opcode
ROXL,ROXR
Destination Rotated with X by count
RTD
(SP)
RTE
If supervisor state
the (SP)
SP + 4
restore state and deallocate stack according to (SP)
else TRAP
RTR
(SP)
(SP)
RTS
(SP)
SBCD
Destination 10 – Source 10 – X
Scc
If Condition True
then 1s
else 0s
STOP
If supervisor state
then Immediate Data
else TRAP
SUB
Destination – Source
SUBA
Destination – Source
SUBI
Destination – Immediate Data
SUBQ
Destination – Immediate Data
SUBX
Destination – Source – X
SWAP
Register [31:16]
TAS
Destination Tested
1
bit 7 of Destination
TBLS
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) *
D
x[7:0]} / 256
TBLSN
ENTRY(n)
Dx [7:0]}
TBLU
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) *
Dx[7:0]} / 256
TBLUN
ENTRY(n) • 256 + {(ENTRY(n + 1) – ENTRY(n)) •
Dx[7:0]}
TRAP
SSP – 2
SSP – 4
SR
TRAPcc
If cc then TRAP
TRAPV
If V then TRAP
TST
Destination Tested
UNLK
An
NOTE 1: d is direction, L or R.
MOTOROLA
Freescale Semiconductor, Inc.
Operation
PC; SP + 4 + d
SP
SR; SP + 2
SP; (SP)
SP;
CCR; SP + 2
SP;
PC; SP + 4
SP
PC; SP + 4
SP
Destination
Destination
Destination
SR; STOP
Destination
Destination
Destination
Destination
Destination
Register [15:0]
Condition Codes;
Dx
256 + {(ENTRY(n + 1) – ENTRY(n)) *
Dx
Dx
Dx
SSP; Format/Offset
SSP; PC
(SSP); SSP – 2
(SSP); Vector Address
PC
Condition Codes
SP; (SP)
An; SP + 4
SP
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Destination ROXd 1 Rx,Dy
ROXd 1 # data ,Dy
ROXd 1 ea
RTD # displacement
RTE
PC;
RTR
RTS
SBCD Dx,Dy
SBCD –(Ax),–(Ay)
Scc ea
STOP # data
SUB ea ,Dn
SUB Dn, ea
SUBA ea ,An
SUBI # data , ea
SUBQ # data , ea
SUBX Dx,Dy
SUBX –(Ax),–(Ay)
SWAP Dn
TAS ea
TBLS. size ea , Dx
TBLS. size Dym:Dyn, Dx
TBLSN. size ea ,Dx
TBLSN. size Dym:Dyn, Dx
TBLU. size ea ,Dx
TBLU. size Dym:Dyn, Dx
TBLUN. size ea ,Dx
TBLUN. size Dym:Dyn,Dx
(SSP);
TRAP # vector
SSP;
TRAPcc
TRAPcc.W # data
TRAPcc.L # data
TRAPV
TST ea
UNLK An
Syntax
5- 19
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