Motorola MC68HC908GP32 Manuals

Manuals and User Guides for Motorola MC68HC908GP32. We have 1 Motorola MC68HC908GP32 manual available for free PDF download: Technical Data Manual

Motorola MC68HC908GP32 Technical Data Manual (410 pages)

Brand: Motorola | Category: Other | Size: 3.7 MB

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32

7
- Table of Contents
  7
Table of Contents

14
Table of Contents

20
- MOTOROLA for more Information on this Product
  24
- Section 1. General Description
  
  33
  - Introduction
    34
  - Features of the CPU08
    36
  - Figure
    37
  - MCU Block Diagram
    37
  - MOTOROLA for more Information on this Product
    38
  - 40-Pin PDIP Pin Assignments
    39
  - 42-Pin SDIP Pin Assignments
    40
  - 44-Pin QFP Pin Assignments
    41
  - Pin Functions
    41
  - External Reset Pin (RST)
    42
  - Power Supply Bypassing
    42
  - Port a Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0)
    43
  - Port C I/O Pins (PTC6–PTC0)
    44
- Section 2. Memory Map
  
  45
- Section 3. Low-Power Modes
  
  59
Low-Power Modes

60
- Introduction
  60
- Stop Mode
  61
- Stop Mode
  62
- Stop Mode
  63
- External Interrupt Module (IRQ)
  64
- Low-Voltage Inhibit Module (LVI)
  65
- Serial Communications Interface Module (SCI)
  65
- Stop Mode
  65
- Wait Mode
  65
- Serial Peripheral Interface Module (SPI)
  66
- Stop Mode
  66
- Timer Interface Module (TIM1 and TIM2)
  66
- Wait Mode
  66
- Exiting Wait Mode
  67
- Stop Mode
  67
- Timebase Module (TBM)
  67
- Wait Mode
  67
- Exiting Stop Mode
  69
Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 4. Resets and Interrupts

71
- Section 4. Resets and Interrupts
  71
  - Effects
    72
  - External Reset
    72
  - Introduction
    72
  - Resets
    72
  - Internal Reset
    73
  - Internal Reset Timing
    73
  - Power-On Reset
    74
  - Power-On Reset Recovery
    74
  - COP Reset
    75
  - Illegal Opcode Reset
    75
  - Low-Voltage Inhibit Reset
    75
  - Illegal Address Reset
    76
  - SIM Reset Status Register
    76
  - SIM Reset Status Register (SRSR)
    76
  - Effects
    77
  - Interrupts
    77
  - Interrupt Stacking Order
    78
  - Interrupt Recognition Example
    79
  - Interrupt Processing
    80
  - Sources
    81
  - Break Interrupt
    82
  - Cgm
    82
  - IRQ Pin
    82
  - SWI Instruction
    82
  - Tim1
    82
  - Spi
    83
  - Tim2
    83
  - Sci
    84
  - ADC (Analog-To-Digital Converter)
    85
  - KBD0-KBD7 Pins
    85
  - TBM (Timebase Module)
    85
  - Interrupt Status Registers
    86
  - Interrupt Status Register 1
    87
  - Interrupt Status Register 1 (INT1)
    87
  - Interrupt Status Register 2
    87
  - Interrupt Status Register 2 (INT2)
    87
  - Interrupt Status Register 3
    88
  - Interrupt Status Register 3 (INT3)
    88
Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 5. Analog-To-Digital Converter (Adc)

89
- Section 5. Analog-To-Digital Converter (ADC)
  89
  - Features
    90
  - Functional Description
    90
  - Introduction
    90
  - ADC Block Diagram
    91
  - ADC Port I/O Pins
    91
  - Conversion
    92
  - Conversion Time
    92
  - Voltage Conversion
    92
  - Accuracy and Precision
    93
  - I/O Signals
    93
  - Interrupts
    93
  - Low-Power Modes
    93
  - Stop Mode
    93
  - Wait Mode
    93
  - ADC Analog Ground Pin (VSSAD )/ ADC Voltage Reference Low Pin (VREFL )
    94
  - ADC Analog Power Pin (VDDAD )/ ADC Voltage Reference High Pin (VREFH )
    94
  - ADC Voltage in (VADIN )
    94
  - I/O Registers
    94
  - ADC Status and Control Register
    95
  - ADC Status and Control Register (ADSCR)
    95
  - ADC Clock Register
    97
  - ADC Clock Register (ADCLK)
    97
  - ADC Data Register
    97
  - ADC Data Register (ADR)
    97
Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 6. Break Module (Brk)

99
- Section 6. Break Module (BRK)
  99
  - Introduction
    99
  - Features
    100
  - Functional Description
    100
  - Break Module Block Diagram
    101
  - I/O Register Summary
    101
  - COP During Break Interrupts
    102
  - CPU During Break Interrupts
    102
  - Flag Protection During Break Interrupts
    102
  - Low-Power Modes
    102
  - TIM1 and TIM2 During Break Interrupts
    102
  - Wait Mode
    102
  - Break Module Registers
    103
  - Break Status and Control Register
    103
  - Break Status and Control Register (BRKSCR)
    103
  - Stop Mode
    103
  - Break Address Register High (BRKH)
    104
  - Break Address Register Low (BRKL)
    104
  - Break Address Registers
    104
  - Break Status Register
    105
  - SIM Break Status Register (SBSR)
    105
  - Break Flag Control Register
    106
  - SIM Break Flag Control Register (SBFCR)
    106
Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 7. Clock Generator Module (Cgmc)

107
- Section 7. Clock Generator Module (CGMC)
  
  107
  - Introduction
    108
  - Features
    109
  - Functional Description
    109
  - CGMC Block Diagram
    110
  - Crystal Oscillator Circuit
    111
  - Phase-Locked Loop Circuit (PLL)
    111
  - PLL Circuits
    111
  - Acquisition and Tracking Modes
    113
  - Manual and Automatic PLL Bandwidth Modes
    113
  - Programming the PLL
    115
  - Base Clock Selector Circuit
    119
  - Special Programming Exceptions
    119
  - CGMC External Connections
    120
  - Crystal Amplifier Input Pin (OSC1)
    121
  - Crystal Amplifier Output Pin (OSC2)
    121
  - I/O Signals
    121
  - External Filter Capacitor Pin (CGMXFC)
    122
  - Oscillator Enable Signal (SIMOSCEN)
    122
  - Oscillator Stop Mode Enable Bit (OSCSTOPENB)
    122
  - PLL Analog Ground Pin (VSSA )
    122
  - PLL Analog Power Pin (VDDA )
    122
  - CGMC Base Clock Output (CGMOUT)
    123
  - CGMC CPU Interrupt (CGMINT)
    123
  - CGMC Registers
    123
  - Crystal Output Frequency Signal (CGMXCLK)
    123
  - CGMC I/O Register Summary
    124
  - PLL Control Register
    125
  - PLL Bandwidth Control Register
    127
  - PLL Bandwidth Control Register (PBWC)
    128
  - PLL Multiplier Select Register High
    129
  - PLL Multiplier Select Register Low
    130
  - PLL VCO Range Select Register
    131
  - PLL Reference Divider Select Register
    132
  - Interrupts
    133
  - Stop Mode
    134
  - Acquisition/Lock Time Specifications
    135
  - Parametric Influences on Reaction Time
    136
  - Choosing a Filter
    137
- Section 8. Configuration Register (CONFIG)
  
  139
  - Configuration Register 2 (CONFIG2)
    140
Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 9. Computer Operating Properly (Cop)

143
- Section 9. Computer Operating Properly (COP)
  143
  - Functional Description
    144
  - Introduction
    144
  - Cgmxclk
    145
  - I/O Signals
    145
  - STOP Instruction
    145
  - COPCTL Write
    146
  - COPD (COP Disable)
    146
  - COPRS (COP Rate Select)
    146
  - Internal Reset
    146
  - Power-On Reset
    146
  - Reset Vector Fetch
    146
  - COP Control Register
    147
  - Interrupts
    147
  - Low-Power Modes
    147
  - Monitor Mode
    147
  - COP Module During Break Mode
    148
  - Stop Mode
    148
  - Wait Mode
    148
Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 10. Central Processor Unit (Cpu)

149
- Section 10. Central Processor Unit (CPU)
  
  149
  - Introduction
    149
  - CPU Registers
    150
  - Features
    150
  - Accumulator
    151
  - Index Register
    152
  - Stack Pointer
    152
  - Program Counter
    153
  - Condition Code Register
    154
  - Arithmetic/Logic Unit (ALU)
    156
  - Low-Power Modes
    156
  - Wait Mode
    156
  - CPU During Break Interrupts
    157
  - Stop Mode
    157
  - Instruction Set Summary
    158
  - Opcode Map
    165
- Section 11. FLASH Memory
  
  167
  - FLASH Control Register
    168
  - FLASH Page Erase Operation
    169
  - FLASH Mass Erase Operation
    170
  - FLASH Program Operation
    171
  - FLASH Block Protection
    172
  - FLASH Programming Flowchart
    173
  - FLASH Block Protect Register
    174
  - Wait Mode
    175
    
    Section 12. External Interrupt (IRQ)
    177
  - Functional Description
    178
  - IRQ Module Block Diagram
    179
  - IRQ Pin
    180
  - IRQ Module During Break Interrupts
    181
  - IRQ Status and Control Register (INTSCR)
    182
- Section 13. Keyboard Interrupt Module (KBI)
  
  183
  - Features
    184
  - Keyboard Initialization
    187
    
    Low-Power Modes
    188
    
    I/O Registers
    189
  - Keyboard Interrupt Enable Register
    190
    
    Section 14. Low-Voltage Inhibit (LVI)
    191
  - Functional Description
    192
  - Polled LVI Operation
    193
  - Forced Reset Operation
    194
  - LVI Status Register
    195
  - LVI Interrupts
    196
- Section 15. Monitor ROM (MON)
  
  197
  - Features
    198
  - Monitor Mode Circuit
    199
  - Entering Monitor Mode
    200
  - Low-Voltage Monitor Mode Entry Flowchart
    203
  - Data Format
    204
  - Baud Rate
    205
  - Read Transaction
    206
  - Security
    210
  - Monitor Mode Entry Timing
    211
Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 16. Input/Output (I/O) Ports

213
- Section 16. Input/Output (I/O) Ports
  
  213
  - Introduction
    214
  - Port a
    217
  - Port a Data Register
    217
  - Data Direction Register a
    218
  - Port a I/O Circuit
    219
  - Port a Input Pullup Enable Register
    220
  - Port B
    221
  - Port B Data Register
    221
  - Data Direction Register B
    222
  - Port C
    224
  - Port C Data Register
    224
  - Data Direction Register C
    225
  - Port C I/O Circuit
    226
  - Port C Input Pullup Enable Register
    227
  - Port D
    228
  - Port D Data Register
    228
  - Data Direction Register D
    230
  - Port D I/O Circuit
    231
  - Port D Input Pullup Enable Register
    232
  - Port E
    232
  - Port E Data Register
    233
  - Data Direction Register E
    234
  - Port E I/O Circuit
    235
- Section 17. Random-Access Memory (RAM)
  
  237
Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 18. Serial Communications Interface Module (Sci)

239
- Module (SCI)
  239
- Features
  240
- Introduction
  240
- Functional Description
  242
- Pin Name Conventions
  242
- SCI Module Block Diagram
  243
- SCI I/O Register Summary
  244
- Data Format
  245
- Transmitter
  245
- SCI Transmitter
  246
- Character Length
  247
- Character Transmission
  247
- Break Characters
  248
- Idle Characters
  248
- Inversion of Transmitted Output
  249
- Transmitter Interrupts
  249
- Character Length
  250
- Character Reception
  250
- Receiver
  250
- SCI Receiver Block Diagram
  251
- Data Sampling
  252
- Baud Rate Tolerance
  254
- Framing Errors
  254
- Slow Data
  255
- Fast Data
  256
- Receiver Wakeup
  257
- Error Interrupts
  258
- Receiver Interrupts
  258
- Low-Power Modes
  259
- Stop Mode
  259
- Wait Mode
  259
- I/O Signals
  260
- Pte0/Txd (Transmit Data)
  260
- SCI During Break Module Interrupts
  260
- I/O Registers
  261
- SCI Control Register 1 (SCC1)
  262
- SCI Control Register 2
  264
- SCI Control Register 2 (SCC2)
  265
- SCI Control Register 3
  267
- SCI Status Register 1
  270
- Flag Clearing Sequence
  273
- SCI Status Register 2
  274
- SCI Data Register
  275
- SCI Baud Rate Register
  276
Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 19. System Integration Module (Sim)

279
- Section 19. System Integration Module (SIM)
  
  279
  - Introduction
    280
  - SIM Block Diagram
    281
  - SIM I/O Register Summary
    282
  - Bus Timing
    283
  - Clock Startup from por or LVI Reset
    283
  - SIM Bus Clock Control and Generation
    283
  - Clocks in Stop Mode and Wait Mode
    284
  - Reset and System Initialization
    284
  - External Pin Reset
    285
  - Active Resets from Internal Sources
    286
  - Power-On Reset
    287
  - Computer Operating Properly (COP) Reset
    288
  - Illegal Address Reset
    288
  - Illegal Opcode Reset
    288
  - Low-Voltage Inhibit (LVI) Reset
    289
  - Monitor Mode Entry Module Reset (MODRST)
    289
  - SIM Counter
    289
  - SIM Counter During Power-On Reset
    289
  - Exception Control
    290
  - Interrupts
    290
  - SIM Counter and Reset States
    290
  - SIM Counter During Stop Mode Recovery
    290
  - Interrupt Entry Timing
    291
  - Interrupt Processing
    292
  - Hardware Interrupts
    293
  - Interrupt Status Registers
    294
  - SWI Instruction
    294
  - Interrupt Status Register 1 (INT1)
    295
  - Break Interrupts
    296
  - Reset
    296
  - Low-Power Modes
    297
  - Status Flag Protection in Break Mode
    297
  - Wait Mode Entry Timing
    298
  - Stop Mode
    299
  - SIM Registers
    300
    
    SIM Reset Status Register
    302
    
    SIM Break Flag Control Register
    303
- Section 20. Serial Peripheral Interface Module (SPI)
  
  305
  - Introduction
    306
  - Pin Name Conventions
    307
  - SPI Module Block Diagram
    308
  - Master Mode
    309
  - Slave Mode
    310
  - Transmission Formats
    311
  - Transmission Format When CPHA = 0
    312
  - Transmission Format (CPHA = 0)
    313
  - Transmission Format When CPHA = 1
    314
  - Transmission Initiation Latency
    315
  - Transmission Start Delay (Master)
    316
  - Queuing Transmission Data
    317
  - Error Conditions
    318
  - Missed Read of Overflow Condition
    319
  - Mode Fault Error
    320
  - Interrupts
    322
  - SPI Interrupt Request Generation
    323
  - Resetting the SPI
    324
  - Low-Power Modes
    325
  - SPI During Break Interrupts
    326
  - MISO (Master In/Slave Out)
    327
  - SPSCK (Serial Clock)
    328
  - CGND (Clock Ground)
    329
  - I/O Registers
    330
  - SPI Status and Control Register
    332
  - SPI Data Register
    335
- Section 21. Timebase Module (TBM)
  
  337
  - Functional Description
    338
  - Timebase Register Description
    339
    
    Interrupts
    340
    
    Low-Power Modes
    341
Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 22. Timer Interface Module (Tim)

343
- Section 22. Timer Interface Module (TIM)
  
  343
  - Features
    344
  - Introduction
    344
  - Functional Description
    345
  - Pin Name Conventions
    345
  - TIM Block Diagram
    346
  - TIM I/O Register Summary
    347
  - Input Capture
    349
  - TIM Counter Prescaler
    349
  - Output Compare
    350
  - Unbuffered Output Compare
    350
  - Buffered Output Compare
    351
  - Pulse Width Modulation (PWM)
    351
  - Unbuffered PWM Signal Generation
    352
  - Buffered PWM Signal Generation
    353
  - PWM Initialization
    354
  - Interrupts
    355
  - Low-Power Modes
    355
  - Stop Mode
    356
  - TIM During Break Interrupts
    356
  - Wait Mode
    356
  - I/O Registers
    357
  - I/O Signals
    357
  - TIM Status and Control Register
    358
  - TIM Counter Registers
    360
  - TIM Counter Modulo Registers
    361
  - TIM Channel Status and Control Registers
    362
  - TIM Channel Registers
    365
  - TIM Channel 0 Register High (TCH0H)
    366
- Section 23. Electrical Specifications
  
  367
  - Introduction
    368
  - Functional Operating Range
    369
  - V DC Electrical Characteristics
    370
  - V DC Electrical Characteristics
    372
  - V Control Timing
    374
  - V Control Timing
    375
  - Output High-Voltage Characteristics
    376
  - Output Low-Voltage Characteristics
    379
  - Typical Supply Currents
    382
  - ADC Characteristics
    384
  - V SPI Characteristics
    385
  - V SPI Characteristics
    386
  - Timer Interface Module Characteristics
    389
  - CGM Electrical Specifications
    390
  - Memory Characteristics
    391
- Section 24. Mechanical Specifications
  
  393
  - Pin Plastic Dual In-Line Package (PDIP)
    394
  - Pin Plastic Quad Flat Pack (QFP)
    395
- Section 25. Ordering Information
  
  397
Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Appendix A. Mc68Hc08Gp32

399
- Appendix A. MC68HC08GP32
  399
  - Introduction
    400
  - MCU Block Diagram
    400
  - Memory Map
    402
    
    A.4 Memory Map
    402
  - Mask Option Registers
    403
  - Monitor ROM
    404
    
    A.6 Reserved Registers
    404
  - Reserved Registers
    404
  - Electrical Specifications
    405
  - Functional Operating Range
    405
  - V DC Electrical Characteristics
    405
    
    A.8 Electrical Specifications
    405
  - V DC Electrical Characteristics
    406
  - Memory Characteristics
    407
  - ROM MC Order Numbers
    408

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Motorola MC68HC908GP32 Technical Data Manual (410 pages)

Table of Contents

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32

Table of Contents

Table of Contents

Section 1. General Description

Section 2. Memory Map

Section 3. Low-Power Modes

Low-Power Modes

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 4. Resets and Interrupts

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 5. Analog-To-Digital Converter (Adc)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 6. Break Module (Brk)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 7. Clock Generator Module (Cgmc)

Section 7. Clock Generator Module (CGMC)

Section 8. Configuration Register (CONFIG)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 9. Computer Operating Properly (Cop)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 10. Central Processor Unit (Cpu)

Section 10. Central Processor Unit (CPU)

Section 11. FLASH Memory

Section 13. Keyboard Interrupt Module (KBI)

Section 15. Monitor ROM (MON)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 16. Input/Output (I/O) Ports

Section 16. Input/Output (I/O) Ports

Section 17. Random-Access Memory (RAM)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 18. Serial Communications Interface Module (Sci)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 19. System Integration Module (Sim)

Section 19. System Integration Module (SIM)

Section 20. Serial Peripheral Interface Module (SPI)

Section 21. Timebase Module (TBM)

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Section 22. Timer Interface Module (Tim)

Section 22. Timer Interface Module (TIM)

Section 23. Electrical Specifications

Section 24. Mechanical Specifications

Section 25. Ordering Information

Technical Data - Mc68Hc908Gp32•Mc68Hc08Gp32 Appendix A. Mc68Hc08Gp32

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