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2.7.3 Data Strobe ( DS )
DS is an output timing signal that applies to the data bus. For a read cycle, the MC68340
asserts DS and AS simultaneously to signal the external device to place data on the bus.
For a write cycle, DS signals to the external device that the data to be written is valid. The
MC68340 asserts DS approximately one clock cycle after the assertion of AS during a
write cycle.
2.7.4 Transfer Size (SIZ1, SIZ0)
These output signals are driven by the bus master to indicate the number of operand
bytes remaining to be transferred in the current bus cycle as noted in Table 2-4.
2.7.5 Read/Write (R/ W )
This active-high output signal is driven by the bus master to indicate the direction of a data
transfer on the bus. A logic one indicates a read from a slave device; a logic zero indicates
a write to a slave device.
2.8 BUS ARBITRATION SIGNALS
The following signals are the bus arbitration control signals used to determine the bus
master. Refer to Section 3 Bus Operation for more information on these signals.
2.8.1 Bus Request ( BR )
This active-low input signal indicates that an external device needs to become the bus
master.
2.8.2 Bus Grant ( BG )
Assertion of this active-low output signal indicates that the MC68340 has relinquished the
bus.
2.8.3 Bus Grant Acknowledge (BGACK)
Assertion of this active-low input indicates that an external device has become the bus
master.
MOTOROLA
Freescale Semiconductor, Inc.
Table 2-4. SIZx Signal Encoding
SIZ1
SIZ0
0
1
1
0
1
1
0
0
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
Transfer Size
Byte
Word
Three Byte
Long Word
2- 7
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