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value of $0 prevents arbitration and causes all SIM40 interrupts, including external
interrupts, to be discarded as extraneous.
4.3.2.2 AUTOVECTOR REGISTER (AVR). The AVR contains bits that correspond to
external interrupt levels that require an autovector response. Setting a bit allows the
SIM40 to assert an internal AVEC during the IACK cycle in response to the specified
interrupt request level. This register can be read and written at any time.
The IARB field in the MCR must contain a value other than $0
for the SIM40 to autovector for external interrupts.
4.3.2.3 RESET STATUS REGISTER (RSR). The RSR contains a bit for each reset source
to the SIM40. A set bit indicates the last type of reset that occurred, and only one bit can
be set in the register. The RSR is updated by the reset control logic when the SIM40
comes out of reset. This register can be read at any time; a write has no effect. For more
information, see Section 3 Bus Operation.
EXT—External Reset
1 = The last reset was caused by an external signal driving RESET .
POW—Power-Up Reset
1 = The last reset was caused by the power-up reset circuit.
SW—Software Watchdog Reset
1 = The last reset was caused by the software watchdog circuit.
DBF—Double Bus Fault Monitor Reset
1 = The last reset was caused by the double bus fault monitor.
Bits 3, 0—Reserved
MOTOROLA
Freescale Semiconductor, Inc.
AVR
7
6
5
4
AV7
AV6
AV5
AV4
RESET:
0
0
0
0
NOTE:
RSR
7
6
5
4
EXT
POW
SW
DBF
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
$006
3
2
1
0
AV3
AV2
AV1
0
0
0
0
0
Supervisor Only
$007
3
2
1
0
0
LOC
SYS
0
Supervisor Only
4- 23
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