11/2/95
LIST OF ILLUSTRATIONS (Continued)
Figure
Number
6-1
DMA Block Diagram............................................................................................... 6-1
6-2
6-3
Dual-Address Transfer........................................................................................... 6-3
6-4
6-5
6-6
Single-Address Read Timing (Cycle Steal)....................................................... 6-9
6-7
Single-Address Write Timing (External Burst)................................................... 6-10
6-8
Single-Address Write Timing (Cycle Steal)....................................................... 6-11
6-9
6-10
Dual-Address Read Timing (Cycle Steal-Source Requesting)................... 6-14
6-11
6-12
Dual-Address Write Timing (Cycle Steal-Destination Requesting)............ 6-17
6-13
6-14
6-15
6-16
7-1
7-2
7-3
Baud Rate Generator Block Diagram.................................................................. 7-8
7-4
7-5
Transmitter Timing Diagram ................................................................................. 7-10
7-6
7-7
Looping Modes Functional Diagram................................................................... 7-15
7-8
Multidrop Mode Timing Diagram ......................................................................... 7-16
7-9
7-10
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
Period Measurement Mode .................................................................................. 8-14
8-10
Event Count Mode.................................................................................................. 8-15
8-11
9-1
9-2
TAP Controller State Machine.............................................................................. 9-3
MOTOROLA
Freescale Semiconductor, Inc.
SECTION 1: OVERVIEW
Title
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
UM Rev 1
P a g e
Number
xix