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CLKOUT
A31–A0
FC3–FC0
SIZ1–SIZ0
AS
DS
R/W
D15–D0
DSACKx
DREQx
DACKx
DONEx
(OUTPUT)
NOTE:
1. To cause another DMA transfer, DREQx is asserted after DACKx is asserted and before
DACKx is negated.
2. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle.
Figure 6-13. Fast Termination Option (Cycle Steal)
If the fast termination option is used with external burst request mode (Figure 6-14), an
extra DMA cycle may result on every burst transfer. Normally, DREQ is negated when
DACK is returned. In the burst mode with fast termination selected, a new cycle starts
even if DREQ is negated simultaneously with DACK assertion.
MOTOROLA
Freescale Semiconductor, Inc.
CPU CYCLE
DMA READ
S0
S2
S4
S0
S4
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
CPU CYCLE
DMA READ
. . . . . . . . . . . . . . . . .
S0
S2
S4
S0
S2
6- 21
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