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J71
PCI-E Slot B x8 (CASwell NIP)-CPU0
J72
PCI-E Slot C x8 (CASwell NIP)-CPU1
J73
PCI-E Slot D x8 (CASwell NIP)-CPU1
(Default Setting:"★")
˙Pin Header definition
JP1(CPU1)：IR PWM IC Programming
JP2(CPU0)：IR PWM IC Programming
Pin No.
Signal Description
1
CLOCK
2
DATA
3
GND
J7/J8/J9/J10：System FAN
1 2 3 4
Pin No.
Signal Description
1
GND
2
12V
3
SENSE
4
PWM Control
J31：PMBus SMBus Connector
J32：PCH SMBus Connector
1 2 3 4 5
Pin No.
Signal Description
1
CLOCK
2
DATA
3
ALERT
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Support Tilera NIP module
Support Tilera NIP module
Support Tilera NIP module
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