Mitsubishi Electric MELSEC Q Series Handbook page 202

7
REPLACEMENT OF PROGRAM
1-bit shift to right of n-bit data
Sub-routine program calls
Special format failure checks
Bit device output reverse
Main  subprogram switching
Pointer branch instruction
Carry flag reset
16-bit data negation transfer
Link Refresh Instructions
BIN 32-bit addition, subtraction
BIN 32-bit multiplication, division
Logical products of 32-bit data
BCD 8-digit addition, subtraction
BCD 8-digit multiplication, division
Conversion from BIN data to 8-digit BCD
Conversion from 8-digit BCD to BIN data
32-bit data negation transfer
32-bit BIN data decrement
16-bit BIN data decrement
8  256-bit decode
2-word data read from the intelligent/special function
module
Interrupt disable instruction
Refresh disable
32-bit BIN data increment
4-bit groupings of 16-bit data
32-bit data transfer
Logical sums of 32-bit data
Left rotation of 32-bit data
Right rotation of 32-bit data
7
- 15
Description
AnSCPU QnUCPU
Instruction name Instruction name Conversion
BSFR BSFR
BSFRP BSFRP
CALL CALL
CALLP CALLP
CHK OUT SM1255
CHK OUT SM1255
CHG OUT SM1255
CJ CJ
CLC OUT SM1255
CML CML
CMLP CMLP
COM COM
D+ D+
D+P D+P
D- D-
D-P D-P
D* D*
D*P D*P
D/ D/
D/P D/P
DAND DAND
DANDP DANDP
DB+ DB+
DB+P DB+P
DB- DB-
DB-P DB-P
DB* DB*
DB*P DB*P
DB/ DB/
DB/P DB/P
DBCD DBCD
DBCDP DBCDP
DBIN DBIN
DBINP DBINP
DCML DCML
DCMLP DCMLP
DDEC DDEC
DDECP DDECP
DEC DEC
DECP DECP
DECO DECO
DECOP DECOP
*1
DFRO
DFRO
*1
DFROP
DFROP
DI DI
DI DI
DINC DINC
DINCP DINCP
DIS DIS
DISP DISP
DMOV DMOV
DMOVP DMOVP
DOR DOR
DORP DORP
DRCL DRCL
DRCLP DRCLP
DRCR DRCR
DRCRP DRCRP
Reference
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Section 7.2.3 (3)
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Section 7.2.3 (1)
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Section 7.2.3 (2)
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Section 7.7.8
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Section 7.2.3 (3)
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 Section 7.7.8
 Section 7.7.8
 Section 7.7.8
 Section 7.7.8