Mitsubishi Electric MELSEC-Q Structured Programming Manual page 99

FXCPU Structured Programming Manual
[Device & Common]
2. Special type data registers
• Special type data registers store specific data in advance, or receive data for special purpose.
The contents of special data registers are set to their initial values when the power is turned ON.
(Generally, these data registers are cleared to "0" first, and then initial values (if there are any) are written
by the system ROM.)
• For example, the watchdog timer time is set initially to D8000 by the system ROM. To change the contents,
write desired time to D8000 using the transfer instruction MOV.
M8002
Initial pulse
→ For the backup characteristics of special data registers, refer to Section 1.2 and Chapter 4.
3. Operation examples
Data registers can be used in various controls handling numeric data.
This paragraph explains representative operation examples among various applications.
For the full use of data registers, refer to the explanation on applied instructions provided later.
1) Specifying the set value of a timer or counter
2) Operation examples using the MOV instruction
a) Changing the current value of a counter
b) Reading the current value of a timer or counter
c) Storing a numeric value in data registers
16-bit type
32-bit type
MOV
EN ENO
s d
K250 D8000
WDT
EN ENO
→ For types and functions of special data registers, refer to Chapter 4.
OUT_T
EN ENO
TCoil
TC2
D0
TValue
OUT_C
EN ENO
CC10 CCoil
D20
CValue
MOV
EN ENO
s d
D5
MOV
EN ENO
s d
CN10
MOV
EN ENO
s d
K200
DMOV
EN ENO
s d
K80000
The watchdog timer is set to 250 ms.
The watchdog timer is refreshed.
A counter or timer operates while regarding the
contents of a specified data register as its set
value.
The current value of the counter C2 is changed to
the contents of D5.
CN2
The current value of the counter C10 is transferred
to D4.
D4
"200 (decimal value)" is transferred to D10.
D10
"80000 (decimal value)" is transferred to D10 and
D11.
Because a numeric value larger than "32767" is
D10
32-bit data, a 32-bit operation is required.
When a data register on the low-order side (D10)
is specified, a data register on the high-order side
(D11) is automatically occupied.
2 Devices in Detail
2.8 Data Register and File Register [D]
1
2
3
4
5
6
7
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