Mitsubishi Electric MELSEC-Q Structured Programming Manual page 62

FXCPU Structured Programming Manual
[Device & Common]
1. Structure of the current value register of a counter
1) 16-bit
High order
0
b15
*1
Sign
0 : Positive
1 : Negative
*1.The sign is valid only when a timer is handled as a substitute for a data register.
2) 32-bit
High order
0
b31
Sign
0 : Positive
1 : Negative
2. Use examples in applied instructions
For the full use of counters as numeric devices, refer to the instruction explanation manual offered separately.
K20000
CN200
60
16-bit
1 0 1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0 1 0
→ FX Structured Programming Manual [Basic & Applied Instruction]
MOV
EN ENO
s d
CN20 D10
CMP
EN ENO
s1 d
K100 M0
s2
CN30
BCD
EN ENO
s d
CN10 K2Y000
MUL_E
EN ENO
_IN
CN5 D4
_IN
K2
DMOV
EN ENO
s d
CN200 D0
DZCP
EN ENO
s1 d
K100 M10
s2
s3
Low order
Available numeric value range
16-bit:0 to 32,767
1 0 1 0 1
b0 32-bit:-2,147,483,648 to +2,147,483,647
32-bit
1 1 1 1 0 0
1 0 1 0 1
CN20 (current value) is transferred to D10.
A decimal integer "100" is compared with CN30
(current value), and the comparison result is
output to M0 to M2.
The contents of CN10 (current value) are converted
into BCD, and output to Y000 to Y007
(to control the 7-segment display unit).
CN5 (current value) is multiplied by "2", and the
obtained value is transferred to (D5, D4).
CN200 (current value) is transferred to (D1, D0).
CN200 (current value) is compared with a decimal
integer zone "100 to 20000", and the comparison
result is output to M10 to M12.
2 Devices in Detail
Low order
0 0 1 1 1 1 0 0 0 0
b0
2.6 Counter [C]