Gtp Transceiver Clock Input Smas; Usb To Uart Bridge - Xilinx SP623 User Manual

GTP Transceiver Clock Input SMAs

[Figure
The SP623 board provides differential SMA connectors that can be used for connecting an
external function generator to all GTP transceiver reference clock inputs of the FPGA. The
FPGA reference clock pins are connected to the SMA connectors as shown in
Table 1-13: GTP Transceiver Clock Inputs to the FPGA

USB to UART Bridge

[Figure
Communications between the SP623 board and a host computer are through a USB Mini-B
cable connected to J9. Control is provided by U26, a USB to UART bridge (Silicon
Laboratories CP2103).
connector J9.
Table 1-14: USB Mini-B Connector Pin Assignments and Signals
SP623 Board User Guide
UG751 (v1.0) May 22, 2010
1-2, callout 18]
FPGA Pin Net Name
B10 101_REFCLK0_P
A10 101_REFCLK0_N
D11 101_REFCLK1_P
C11 101_REFCLK1_N
D15 123_REFCLK0_P
C15 123_REFCLK0_N
B16 123_REFCLK1_P
A16 123_REFCLK1_N
AE11 245_REFCLK0_P
AF11 245_REFCLK0_N
AC12 245_REFCLK1_P
AD12 245_REFCLK1_N
AC16 267_REFCLK0_P
AD16 267_REFCLK0_N
AE17 267_REFCLK1_P
AF17 267_REFCLK1_N
1-2, callout 19]
Table 1-14
J9 Pin Signal Name
1 VBUS
2 USB_DATA_N Bidirectional differential serial data (N-side)
3 USB_DATA_P
4 GROUND
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SMA Connector
J59
J60
J49
J50
J70
J61
J72
J71
J80
J81
J82
J83
J92
J93
J94
J95
lists the pin assignments and signals for the USB
Description
+5V from host system (not used)
Bidirectional differential serial data (P-side)
Signal ground
Detailed Description
Table 1-13.
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