Xilinx SP623 User Manual page 18

Chapter 1: SP623 Board Features and Operation
Table 1-6: SuperClock-2 FPGA I/O Mapping
18
FPGA Pin Net Name
F12 CM_LVDS1_P
E12 CM_LVDS1_N
V12 CM_LVDS2_P
W12 CM_LVDS2_N
G12 CM_LVDS3_P
F11 CM_LVDS3_N
U25 CM_GCLK_P
U26 CM_GCLK_N
U20 CM_CTRL_0
U19 CM_CTRL_1
AA24 CM_CTRL_2
AA23 CM_CTRL_3
T20 CM_CTRL_4
T19 CM_CTRL_5
U22 CM_CTRL_6
U21 CM_CTRL_7
AE26 CM_CTRL_8
AE25 CM_CTRL_9
Y26 CM_CTRL_10
Y24 CM_CTRL_11
AC26 CM_CTRL_12
AC25 CM_CTRL_13
AB26 CM_CTRL_14
AB24 CM_CTRL_15
AD26 CM_CTRL_16
AD24 CM_CTRL_17
AA26 CM_CTRL_18
AA25 CM_CTRL_19
W26 CM_CTRL_20
W25 CM_CTRL_21
V24 CM_CTRL_22
T23 CM_CTRL_23
T22 CM_RST
www.xilinx.com
J32 Pin
1
3
9
11
17
19
25
27
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
66
SP623 Board User Guide
UG751 (v1.0) May 22, 2010