Gtp Transceiver Pins - Xilinx SP623 User Manual

GTP Transceiver Pins

[Figure
All FPGA GTP transceiver pins are connected to differential SMA connector pairs. The
GTP transceivers are grouped into four sets of two (referred to as Duals) which share two
differential reference clock pin-pairs
corresponding SMA connector are identified in
X-Ref Target - Figure 1-8
Figure 1-8: GTP Transceiver and Reference Clock SMA Locations
Table 1-12: GTP Transceiver Pins
SP623 Board User Guide
UG751 (v1.0) May 22, 2010
1-2, callout 17]
123 Clocks Dual 123
101 Clocks Dual 101
FGPA Pin
D7
C7
B6
A6
D9
C9
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(Figure 1-8). The transceiver pins and their
Table
Dual 267 267 Clocks
Dual 245 245 Clocks
Net Name SMA Connector
101_RX0_P
101_RX0_N
101_TX0_P
101_TX0_N
101_RX1_P
101_RX1_N
Detailed Description
1-12.
UG751_c1_07_052210
Trace Length (Mils)
J51 4,253
J52 4,253
J53 3,634
J54 3,633
J55 3,861
J56 3,861
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