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Table 1-17: Vita 57.1 FMC1 HPC Connections at J112 (Cont'd)
Notes:
1. This signal is not directly connected to the FPGA. The value in the
Table 1-18: Vita 57.1 FMC2 HPC Connections at J113
SP623 Board User Guide
UG751 (v1.0) May 22, 2010
FPGA Pin
Net Name
E5
FMC1_LA33_N
E3
FMC1_PRSNT_M2C
U20.13
FMC1_TCK_BUF
(1)
J36.1
FMC1_TDI
J36.3
FMC1_TDO
(1)
U20.16
TMS_BUF
leftmost column represents the device and pin the signal is
connected to. For example, U14.13 = U14 pin 13.
FPGA Pin
Net Name
U23
FMC2_CLK0_M2C_P
U24
FMC2_CLK0_M2C_N
AD14
FMC2_CLK1_M2C_P
AF14
FMC2_CLK1_M2C_N
R7
FMC2_HA00_CC_P
R6
FMC2_HA00_CC_N
U4
FMC2_HA02_P
U3
FMC2_HA02_N
V5
FMC2_HA03_P
W5
FMC2_HA03_N
U9
FMC2_HA04_P
U8
FMC2_HA04_N
U7
FMC2_HA05_P
T6
FMC2_HA05_N
AB3
FMC2_HA06_P
AB1
FMC2_HA06_N
AD3
FMC2_HA07_P
AD1
FMC2_HA07_N
AC2
FMC2_HA08_P
AC1
FMC2_HA08_N
AE2
FMC2_HA09_P
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FMC Pin
G37
H2
(1)
D29
D30
(1)
D31
D33
FMC Pin
H4
H5
G2
G3
F4
F5
K7
K8
J6
J7
F7
F8
E6
E7
K10
K11
J9
J10
F10
F11
E9
Detailed Description
29
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