I 2 C Bus Management - Xilinx SP623 User Manual

Table 1-18: Vita 57.1 FMC2 HPC Connections at J113 (Cont'd)
Notes:
1. This signal is not directly connected to the FPGA. The value in the
Table 1-19: Power Supply Voltages for the HPC Connector
2
I C Bus Management
[Figure
The I
Instruments PCA9544A). The FPGA communicates with the multiplexer through I
and clock signals mapped to FPGA pins J24 and J23, respectively. The I
PCA9544A device is 0x70. The bus hosts four components:
•
•
•
•
An I
control register of the MUX as shown in
Table 1-20: I
Channel
SP623 Board User Guide
UG751 (v1.0) May 22, 2010
FPGA Pin Net Name
AC3 FMC2_PRSNT_M2C
U20.13 FMC2_TCK_BUF
J36.1 FMC2_TDI
J36.3 FMC2_TDO
U20.16 TMS_BUF
leftmost column represents the device and pin the signal is
connected to. For example, U14.13 = U14 pin 13.
Voltage Allowable
Supply Voltage Range
V Fixed 2.5V
ADJ
3P3V 3.3V
AUX
3P3V 3.3V
12P0V 12V
1-2, callout 21]
2
C bus is controlled through U14, a four-channel I
SuperClock-2 module
GTP Transceiver power supply module
FMC1
FMC2
2
C component can be accessed by selecting the appropriate channel through the
2
C Channel Assignments
U27
2
I C Component
0 SuperClock-2 module
1 GTP transceiver power supply module
2 FMC1
3 FMC2
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FMC Pin
H2
(1)
D29
(1)
D30
(1)
D31
(1)
D33
Number Maximum
of Pins Amps
4 4
1 0.020
4 3
2 1
Table 1-20.
Detailed Description
Maximum
Tolerance
Capacitive Load
±5% 1,000 µF
±5% 150 µF
±5% 1,000 µF
±5% 1,000 µF
2
C-bus multiplexer (Texas
2
C idcode for the
2
C data
33