Differential Clock Input And Output With Sma Connectors (31) - Xilinx SP305 Spartan-3 User Manual

SP305 Spartan-3 Development Platform User Guide
Table 2-21: VGA FPGA Pins

Differential Clock Input And Output With SMA Connectors (31)

High-precision clock signals can be input to the FPGA using differential clock signals
brought in through 50Ω SMA connectors, thereby allowing an external function generator
or other clock source to drive the differential clock inputs that directly feed the global clock
input pins of the FPGA. The FPGA can be configured to present a 100Ω termination
impedance.
22
Label
VGA_B4
VGA_B5
VGA_B6
VGA_B7
VGA_R0
VGA_R1
VGA_R2
VGA_R3
VGA_R4
VGA_R5
VGA_R6
VGA_R7
VGA_G0
VGA_G1
VGA_G2
VGA_G3
VGA_G4
VGA_G5
VGA_G6
VGA_G7
VGA_BLANK_N
VGA_PSAVE_N
VGA_SYNC_N
VGA_VSYNC_N
VGA_HSYNC_N
VGA_CLK
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FPGA Pin
K1
K2
K3
K4
H11
B10
A10
H3
H4
J6
H5
G1
G11
F11
E11
J5
K7
J7
H1
H2
H12
G12
H13
D1
E4
F6
SP305 Spartan-3 Development Platform User Guide
Description
Blue 4
Blue 5
Blue 6
Blue 7
4.7K to GND
4.7K to GND
4.7K to GND
Red 3
Red 4
Red 5
Red 6
Red 7
4.7K to GND
4.7K to GND
4.7K to GND
Green 3
Green 4
Green 5
Green 6
Green 7
Blank
Psave
Sync
Vsync
Hsync
VGA clock
UG216 (v1.1) March 3, 2006
R