Table of Contents
Advertisement
Chapter 1: SP623 Board Features and Operation
Linear Technology Module is installed, place jumpers on JP1 and/or JP2 across pins 2–3
(OFF position).
Note:
external supply to its corresponding supply jack.
The Texas Instruments module does not have voltage regulation jumpers and must be
removed from the board before providing external power to the GTP transceiver rails.
MGTAVCCPLL Rail
The GTP transceiver power module also supplies the MGTAVCCPLL rail through the J3
shorting plug
default. The MGTAVCCPLL rail can also be supplied from an external 1.2V (nominal)
power supply by removing the J3 shorting plug and then connecting the power supply
output to J5.
X-Ref Target - Figure 1-5
FPGA Configuration
[Figure
The FPGA is configured in JTAG mode only using one of the following options:
•
•
•
•
Detailed information on the System ACE controller is available in
DS080, System ACE CompactFlash Solution.
The FPGA is configured through one of the aforementioned cables by connecting the cable
to the download cable connector, J1.
The FPGA is configured through the System ACE controller by setting the 3-bit
configuration address DIP switches (SW3) to select one of eight bitstreams stored on a
CompactFlash memory card (see
Note:
cable is used, causing no disruption in the JTAG chain.
14
The power regulation jumper must be placed in the OFF position before connecting an
(Figure
1-5). This jumper connects MGTAVCC and MGTAVCCPLL rails by
12V DC
GTP Power
VCC5
Supply Module
VCC3V3
Figure 1-5: MGTAVCCPLL Isolation Jumper
1-2, callout 2]
Platform Cable USB
Parallel Cable IV
Parallel Cable III
System ACE controller
The System ACE controller is bypassed when the flying wire leads or the Parallel Cable IV
www.xilinx.com
MGTAVCC
MGTAVTT
J3
Configuration Address DIP Switches, page
External Supply Jacks
J5
J178
J189
MGTAVCCPLL
UG751_c1_05_041910
16).
SP623 Board User Guide
UG751 (v1.0) May 22, 2010
Advertisement
Table of Contents
