Xilinx SP623 User Manual page 39

SP623 Master UCF Listing
The SP623 master user constraints file (UCF) template provides for designs targeting the
SP623 Spartan-6 FPGA GTP transceiver characterization board. Net names in the
constraints listed below correlate with net names on the SP623 board schematic. Users
must identify the appropriate pins and replace the net names below with net names in the
user RTL. See the
Users can refer to the UCF files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O
standards information required for each particular interface. The FMC connectors J112 and
J113 are connected to 2.5V V
customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by each
customer.
SP623 Master UCF Listing:
SP623 Board User Guide
UG751 (v1.0) May 22, 2010
Constraints Guide
cco
NET "101_REFCLK0_N
NET "101_REFCLK0_P
NET "101_REFCLK1_N
NET "101_REFCLK1_P
NET "101_RX0_N
NET "101_RX0_P
NET "101_RX1_N
NET "101_RX1_P
NET "101_TX0_N
NET "101_TX0_P
NET "101_TX1_N
NET "101_TX1_P
NET "123_REFCLK0_N
NET "123_REFCLK0_P
NET "123_REFCLK1_N
NET "123_REFCLK1_P
NET "123_RX0_N
NET "123_RX0_P
NET "123_RX1_N
NET "123_RX1_P
NET "123_TX0_N
NET "123_TX0_P
NET "123_TX1_N
NET "123_TX1_P
NET "245_REFCLK0_N
NET "245_REFCLK0_P
NET "245_REFCLK1_N
NET "245_REFCLK1_P
NET "245_RX0_N
NET "245_RX0_P
NET "245_RX1_N
www.xilinx.com
for more information.
banks. Because each user's FMC card implements
"LOC = "A10";
"LOC = "B10";
"LOC = "C11";
"LOC = "D11";
"LOC = "C7";
"LOC = "D7";
"LOC = "C9";
"LOC = "D9";
"LOC = "A6";
"LOC = "B6";
"LOC = "A8";
"LOC = "B8";
"LOC = "C15";
"LOC = "D15";
"LOC = "A16";
"LOC = "B16";
"LOC = "C17";
"LOC = "D17";
"LOC = "C19";
"LOC = "D19";
"LOC = "A18";
"LOC = "B18";
"LOC = "A20";
"LOC = "B20";
"LOC = "AF11";
"LOC = "AE11";
"LOC = "AD12";
"LOC = "AC12";
"LOC = "AD8";
"LOC = "AC8";
"LOC = "AD10";
Appendix C
39