External Memory Expansion - NEC UPD703116 User Manual

(4) External memory area
256 MB are available for external memory area. The lower 64 MB can be used as program/data area and the
higher 192 MB as data area.
• When in single-chip mode 0:
• When in single-chip mode 1:
• When in ROMless modes 0 and 1: x0000000H to xFFFBFFFH
Access to the external memory area uses the chip-select signal assigned to each memory block (which is
carried out in the CS unit set by chip area selection control registers 0 and 1 (CSC0, CSC1)).
Note that, the internal ROM, internal RAM, on-chip peripheral I/O, and programmable peripheral I/O areas
cannot be accessed as external memory areas.
3.4.6

External memory expansion

By setting the port n mode control register (PMCn) to control mode, an external device can be connected to the
external memory space using each pin of ports DH, DL, CS, CT, and CM. Each register is set by selecting control
mode for each pin of these ports using PMCn (n = DH, DL, CS, CT, CM).
Note that the status after reset differs as shown below in accordance with the operating mode specification set by
pins MODE0 to MODE2 (refer to 3.3 Operation Modes for details of the operation modes).
(a) In the case of ROMless mode 0
Because each pin of ports DH, DL, CS, CT, and CM enters control mode following a reset, external
memory can be used without making changes to the port n mode control register (PMCn) (the external
data bus width is 16 bits).
(b) In the case of ROMless mode 1
Because each pin of ports DH, DL, CS, CT, and CM enters control mode following a reset, external
memory can be used without making changes to the port n mode control register (PMCn) (the external
data bus width is 8 bits).
(c) In the case of single-chip mode 0
Since the internal ROM area is accessed after a reset, each pin of ports DH, DL, CS, CT, and CM enters
the port mode, and external devices cannot be used.
To use external memory, set the port n mode control register (PMCn).
(d) In the case of single-chip mode 1
The internal ROM area is allocated from address 100000H. As a result, because each pin of ports DH,
DL, CS, CT, and CM enters control mode following a reset, external memory can be used without making
changes to the port n mode control register (PMCn) (the external data bus width is 16 bits).
Remark n = DH, DL, CS, CT, CM
CHAPTER 3 CPU FUNCTION
x0100000H to xFFFBFFFH
x0000000H to x00FFFFFH, x0200000H to xFFFBFFFH
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