NEC UPD703116 User Manual page 322

(d) Operation in UDC mode B
(i) Basic operation
The operations at the next count clock after the count value of TM1n and the CM1n0 set value match
when TM1n is in UDC mode B are as follows.
• In case of up-count operation: TM1n is cleared (0000H) and the INTCM1n0 interrupt is generated.
• In case of down-count operation: The TM1n count value is decremented (−1).
The operations at the next count clock after the count value of TM1n and the CM1n1 set value match
when TM1n is in UDC mode B are as follows.
• In case of up-count operation: The TM1n count value is incremented (+1).
• In case of down-count operation: TM1n is cleared (0000H) and the INTCM1n1 interrupt is
generated.
CM1n0 set value
TM1n count value
CM1n1 set value
Remark n = 0, 1
(ii) Compare function
TM1n connects two compare register (CM1n0, CM1n1) channels and two capture/compare register
(CC1n0, CC1n1) channels.
When the TM1n count value and the set value of one of the compare registers match, a match
interrupt (INTCM1n0 (only during up-count operation), INTCM1n1 (only during down-count
operation), INTCC1n0
Note This match interrupt is generated when CC1n0 and CC1n1 are set to the compare register
mode.
(iii) Capture function
TM1n connects two capture/compare register (CC1n0, CC1n1) channels.
When CC1n0 and CC1n1 are set to the capture register mode, the value of TM1n is captured in
synchronization with the corresponding capture trigger signal.
INTCC1n1) is generated upon detection of the valid edge.
322
CHAPTER 9 TIMER/COUNTER FUNCTION
Figure 9-58. Example of TM1n Operation in UDC Mode
Clear TM1n not
cleared if count clock
counts down following match
Note Note
, INTCC1n1 ) is output.
User's Manual U14492EJ5V0UD
TM1n not
cleared if count clock
Clear counts up following match
A capture interrupt (INTCC1n0,