NEC UPD703116 User Manual page 56

(6) Exception/debug trap status saving registers (DBPC, DBPSW)
There are two exception/debug trap status saving registers, DBPC and DBPSW.
Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to
DBPC, and the program status word (PSW) contents are saved to DBPSW.
The contents saved to DBPC consist of the address of the next instruction after the instruction executed when
an exception trap or debug trap occurs.
The current PSW contents are saved to DBPSW.
These registers can be read or written only in the period between DBTRAP instruction execution and DBRET
instruction execution.
Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved (fixed to 0) for future function expansion.
When the DBRET instruction has been executed, the values of DBPC and DBPSW are restored to the PC
and PSW, respectively.
31
DBPC
0 0 0 0 0 0
31
DBPSW
0 0 0 0 0 0
(7) CALLT base pointer (CTBP)
The CALLT base pointer (CTBP) is used to specify table addresses and generate target addresses (bit 0 is
fixed to 0).
Bits 31 to 26 are reserved (fixed to 0) for future function expansion.
31
CTBP
0 0 0 0 0 0
56
CHAPTER 3 CPU FUNCTION
26 25
(PC contents saved)
0 0 0 0 0 0 0 0 0 0 0 0
26 25
User's Manual U14492EJ5V0UD
8 7
0 0 0 0 0 0 (PSW contents saved)
(Base address)
0
After reset
0xxxxxxxH
(x: Undefined)
0
After reset
000000xxH
(x: Undefined)
0
After reset
0
0xxxxxxxH
(x: Undefined)