NEC UPD703116 User Manual page 170

32-bit single-chip microcontrollers
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Figure 7-6. Example of Servicing in Which Another Interrupt Request Is Issued While an
Interrupt Is Being Serviced (2/2)
Main routine
Interrupt request i
(level 2)
Interrupt request l
(level 2)
Interrupt request o
(level 3)
Interrupt request s
(level 1)
Caution The values of the EIPC and EIPSW registers must be saved before executing multiple
interrupts. When returning from multiple interrupt servicing, restore the values of EIPC
and EIPSW after executing the DI instruction.
170
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Servicing of i
EI
EI
Interrupt
request j
(level 3)
Interrupt request k
(level 1)
Servicing of j
Servicing of l
Interrupt
request m
(level 3)
Interrupt request n
(level 1)
Servicing of n
Servicing of m
Servicing of o
EI
EI
Interrupt
Interrupt
request p
request q
(level 2)
(level 1)
Servicing of s
Interrupt
request t
Note 1
(level 2)
Interrupt request u
Note 2
(level 2)
Servicing of u
Servicing of t
User's Manual U14492EJ5V0UD
Servicing of k
Interrupt request j is held pending because its
priority is lower than that of i.
k that occurs after j is acknowledged because it
has the higher priority.
Interrupt requests m and n are held pending
because servicing of l is performed in the interrupt
disabled status.
Pending interrupt requests are acknowledged after
servicing of interrupt request l.
At this time, interrupt requests n is acknowledged
first even though m has occurred first because the
priority of n is higher than that of m.
Servicing of p
Servicing of q
Servicing of r
EI
Interrupt
request r
(level 0)
If levels 3 to 0 are acknowledged
Pending interrupt requests t and u are
acknowledged after servicing of s.
Because the priorities of t and u are the same, u is
acknowledged first because it has the higher
default priority, regardless of the order in which the
interrupt requests have been generated.
Notes 1.
2.
Lower default priority
Higher default priority

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