NEC UPD703116 User Manual page 327

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Interrupt request sources
• Compare-match interrupt request: 6 types
Perform comparison with sub-channel n capture/compare register and generate the INTCC2n interrupt upon
compare match.
• Timer/counter overflow interrupt request: 2 types
The INTTM20 (INTTM21) interrupt is generated when the count value of TM20 (TM21) becomes FFFFH.
•
Capture request
The count values of TM20, TM21 can be latched using external pin (INTP2n)
signals (INTCM100, INTCM101) and interrupt requests by software as capture triggers.
•
PWM output function
Control of the outputs of pins TO21 to TO24 in the compare mode and PWM output can be performed using
the compare match timing of sub-channels 1 to 4 and the zero count signal of the timer/counter.
•
Timer count operation with external clock input
Timer count operation can be performed with the pin TI2 clock input signal.
•
Timer count enable operation
Timer count enable operation can be performed with the TCLR2 pin input signal.
•
Timer/counter clear operation
Timer/counter clear operation can be performed with the TCLR2 pin input signal.
•
Notes 3, 5
Up/down count control
Up/down count operation in the compare mode can be controlled with the TCLR2 pin input signal.
•
Output delay operation
A clock-synchronized output delay can be added to the output signal of pins TO21 to TO24.
This is effective as an EMI countermeasure.
•
Input filter
An input filter can be inserted at the input stage of external pins (TI2, INTP20 to INTP25, TCLR2) and the
TM10, TM11 interrupt signals (refer to 14.5.3 (1) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5)).
Notes 1. For the registers used to specify the valid edge for external interrupt requests (INTP20 to INTP25) to
timer 2, refer to 7.3.8 (4) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5).
2. The pairs TI2 and INTP20, TO21 and INTP21, TO22 and INTP22, TO23 and INTP23, TO24 and
INTP24, TCLR2 and INTP25 are each alternate function pins.
3. The count enable operation for the timer/counter through external pin input, timer/counter clear
operation, and up/down count control cannot be performed combined all at the same time.
4. In the case of 32-bit cascade connection, clear operation by external pin input (TCLR2) cannot be
performed.
5. Up/down count control using 32-bit cascade connection cannot be performed.
Remark f : Internal system clock
XX
n = 0 to 5
CHAPTER 9 TIMER/COUNTER FUNCTION
Note 2
Note 3
with external pin input
Notes 3, 4
with external pin input
Note 2
with external pin input
User's Manual U14492EJ5V0UD
Notes 1, 2
Note 2
Note 2
, TM10, TM11 interrupt
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