NEC UPD703116 User Manual page 40

(v) CRXD (Receive data for controller area network) ... Input
This pin inputs FCAN serial receive data.
(6) PCM0 to PCM4 (Port CM) ... I/O
Port CM is a 5-bit I/O port in which input or output can be set in 1-bit units.
Besides functioning as a port, in control mode, PCM0 to PCM4 operate as wait insertion signal input, internal
system clock output, and bus hold control signal output.
An operation mode of port or control mode can be selected for each bit and specified by the port CM mode
control register (PMCCM).
(a) Port mode
PCM0 to PCM4 can be set to input or output in 1-bit units using the port CM mode register (PMCM).
(b) Control mode
PCM0 to PCM4 can be set to port or control mode in 1-bit units using PMCCM.
(i) WAIT (Wait) ... Input
This control signal input pin, which inserts a data wait in a bus cycle, can input asynchronously with
respect to a CLKOUT signal. Sampling is done at the falling edge of a CLKOUT signal in a bus cycle
in a T2 or TW state. If the setup or hold time is not secured in the sampling timing, wait insertion
may not be performed.
(ii) CLKOUT (Clock output) ... Output
This is an internal system clock output pin. In single-chip mode 1 and ROMless mode 0 or 1, output
is not performed by the CLKOUT pin because it is in port mode during the reset period. To perform
CLKOUT output, set this pin to control mode using the port CM mode control register (PMCCM).
(iii) HLDAK (Hold acknowledge) ... Output
This is an acknowledge signal output pin that shows that the V850E/IA1 received a bus hold request
and that the external address/data bus and various strobe pins entered in a high-impedance state.
While this signal is active, the external address/data bus and various strobe pins become high-
impedance and transfer the bus mastership to the external bus master.
(iv) HLDRQ (Hold request) ... Input
This is the input pin by which an external device requests that the V850E/IA1 release the external
address/data bus and various strobe pins. The signal via this pin can be input asynchronously with
respect to the CLKOUT signal. When this pin becomes active, the V850E/IA1 makes the external
address/data bus and various strobe pins high-impedance after the executing bus cycle terminates
(or immediately if there is none) and releases the bus by making the HLDAK signal active.
To reliably set bus hold status, keep the HLDRQ signal active until a HLDAK signal is output.
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CHAPTER 2 PIN FUNCTIONS
User's Manual U14492EJ5V0UD