Cautions On Use - NEC UPD703116 User Manual

11.16 Cautions on Use

<1> Bit manipulation is prohibited for all FCAN controller registers.
<2> Be sure to properly clear (0) all interrupt request flags
cleared (0), subsequent interrupt requests may not be generated. Note also that if an interrupt is generated
at the same time as a CPU clear operation, that interrupt request flag will not be cleared (0). It is therefore
important to confirm that interrupt request flags have been properly cleared (0).
Note See 11.10 (10) CAN interrupt pending register (CCINTP), 11.10 (11) CAN global interrupt
pending register (CGINTP), and 11.10 (12) CAN1 interrupt pending register (C1INTP).
<3> When a change occurs on the CAN bus via a setting of the CSTP bit in the CSTOP register while the clock
supply to the CPU or peripheral functions is stopped, the CPU can be woken up.
<4> Do not read the same register of the FCAN controller twice or more in a row. If the same register is read
twice or more in a row, and even if the value of the register is changed while it is being read the second or
subsequent time, the new value is not reflected, and the same value as the one read the first time is always
read.
Example Reading the C1CTRL and C1BA registers
(i)
(ii) Incorrect usage: The second read value of C1CTRL is the same as the first read value of
<5> When receiving a remote frame with an extended ID and storing it in the receive message buffer, the values
of DLC3 to DLC0 in the message buffer are cleared to 0 regardless of the values of DLC3 to DLC0 on the
CAN bus.
CHAPTER 11 FCAN CONTROLLER
Correct usage: New value is reflected when C1CTRL is read the second time.
C1CTRL read
C1BA read
C1CTRL read
C1CTRL.
C1CTRL read
C1CTRL read
C1BA read
User's Manual U14492EJ5V0UD
Note
in the interrupt routine. If these flags are not
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