NEC UPD703116 User Manual page 501

32-bit single-chip microcontrollers
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Figure 10-29. Repeat Transfer (Receive-Only) Timing Chart
SCKn (I/O)
SIn (input)
din-1
SIOLn
register
SIRBLn
register
Reg_RD
SIRBn (dummy)
CSOTn bit
INTCSIn
interrupt
SOn (output)
L
rq_clr
trans_rq
<1>
<2>
<3>
Remarks 1. n = 0, 1
2. Reg_RD:
Internal signal. This signal indicates that the receive data buffer register (SIRBn/
SIRBLn) has been read.
rq_clr: Internal signal. Transfer request clear signal.
trans_rq: Internal signal. Transfer request signal.
In the case of the repeat transfer mode, two transfer requests are set at the start of the first transfer.
Following the transmission/reception completion interrupt request (INTCSIn), transfer is continued if the
SIRBn register can be read within the next transfer reservation period. If the SIRBn register cannot be
read, transfer ends and the SIRBn register does not receive the new value of the SIOn register.
The last data can be obtained by reading the SIOn register following completion of the transfer.
CHAPTER 10 SERIAL INTERFACE FUNCTION
din-2
din-3
din-1
din-2
SIRBn (d1)
<4>
<3>
<4> <3>
<5>
Period during
which next transfer
can be reserved
User's Manual U14492EJ5V0UD
din-4
din-3
din-4
SIRBn (d2)
SIRBn (d3)
<4>
din-5
din-5
SIRBEn (d4)
SIOn (d5)
<6>
501

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