Register Controlling Clock Monitor - NEC 78K0/KD1 Series User Manual

20.3 Register Controlling Clock Monitor

Clock monitor is controlled by the clock monitor mode register (CLM).
(1) Clock monitor mode register (CLM)
This register sets the operation mode of the clock monitor.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Address: FFA9H After reset: 00H
Symbol 7
CLM 0
CLME
0
1
Cautions 1. Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or the internal
reset signal.
2. If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1 (CLMRF)
of the reset control flag register (RESF) is set to 1. CLMRF is read by software and then
automatically cleared to 0. CLMRF is cleared under the following conditions.
• • • •
RESET input
• • • •
Internal reset signal generation by POC
• • • •
After read by software
CHAPTER 20 CLOCK MONITOR
Figure 20-2. Format of Clock Monitor Mode Register (CLM)
R/W
6 5
0 0
Enables/disables clock monitor operation
Disables clock monitor operation
Enables clock monitor operation
Preliminary User's Manual U16315EJ1V0UD
4 3 2
0 0 0
1 0
0 CLME
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