Registers Controlling Watchdog Timer - NEC 78K0/KD1 Series User Manual

10.3 Registers Controlling Watchdog Timer

The watchdog timer is controlled by the following two registers.
• Watchdog timer mode register (WDTM)
• Watchdog timer enable register (WDTE)
(1) Watchdog timer mode register (WDTM)
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
RESET input sets this register to 67H.
Figure 10-2. Format of Watchdog Timer Mode Register (WDTM)
Address: FF98H After reset: 67H
7
Symbol
0
WDTM
Note 1
WDCS4 WDCS3
0
0
1
Note 2
WDCS2 WDCS1
0
0
0
0
1
1
1
1
Notes 1. If "Ring-OSC cannot be stopped" is specified by a mask option, this cannot be set. The Ring-
OSC clock will be selected no matter what value is written.
2. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
Cautions 1. If data is written to WDTM, a wait cycle is generated. Do not write data to WDTM
when the CPU is operating on the subsystem clock and the X1 input clock is
stopped. For details, refer to CHAPTER 29 CAUTIONS FOR WAIT.
2. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when "Ring-OSC cannot be stopped"
is selected by a mask option, other values are ignored).
212
CHAPTER 10 WATCHDOG TIMER
R/W
6 5 4
1 1 WDCS4
Note 1
0 Ring-OSC clock (f )
R
1 X1 input clock (f )
XP
×
Watchdog timer operation stopped
Note 2 Note 2
WDCS0
During Ring-OSC clock
11
0 0 f /2 (8.53 ms)
R
12
0 1 f /2 (17.07 ms)
R
13
1 0 f /2 (34.13 ms)
R
14
1 1 f /2 (68.27 ms)
R
15
0 0 f /2 (136.53 ms)
R
16
0 1 f /2 (273.07 ms)
R
17
1 0 f /2 (546.13 ms)
R
18
1 1 f /2 (1.09 s)
R
Preliminary User's Manual U16315EJ1V0UD
3 2
WDCS3 WDCS2
Operation clock selection
Overflow time setting
During X1 input clock operation
operation
(819.2 µ s)
13
f /2
XP
14
f /2 (1.64 ms)
XP
15
f /2 (3.28 ms)
XP
16
f /2 (6.55 ms)
XP
17
f /2 (13.11 ms)
XP
18
f /2 (26.21 ms)
XP
19
f /2 (52.43 ms)
XP
20
f /2 (104.86 ms)
XP
1 0
WDCS1 WDCS0