Configuration Of A/D Converter - NEC 78K0/KD1 Series User Manual

12.2 Configuration of A/D Converter

The A/D converter consists of the following hardware.
Analog input
Registers
Control registers
(1) Successive approximation register (SAR)
This register compares the analog input voltage value with the voltage tap (compare voltage) value applied from
the series resistor string, and holds the result starting from the most significant bit (MSB).
When the result up to the least significant bit (LSB) is held (end of A/D conversion), the SAR contents are
transferred to the A/D conversion result register.
(2) A/D conversion result register (ADCR)
The ADCR is 16-bit register that stores the A/D conversion result. The lower six bits are fixed to 0. Each time
A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in
ADCR in order starting from the most significant bit (MSB).
ADCR can be read by a 16-bit memory manipulation instruction.
RESET input makes ADCR undefined.
Address: FF08H, FF09H
Symbol
ADCR
Cautions 1. When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined.
conversion result following conversion completion before writing to ADM and ADS. Using
timing other than the above may cause an incorrect conversion result to be read.
2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the
CPU is operating on the subsystem clock and the X1 input clock is stopped. For details,
refer to CHAPTER 29 CAUTIONS FOR WAIT.
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CHAPTER 12 A/D CONVERTER
Table 12-1. Configuration of A/D Converter
Item
8 channels (ANI0 to ANI7)
Successive approximation register (SAR)
A/D conversion result register (ADCR)
A/D converter mode register (ADM)
Analog input channel specification register (ADS)
Power-fail comparison mode register (PFM)
Power-fail comparison threshold register (PFT)
Figure 12-3. Format of A/D Conversion Register (ADCR)
After reset: Undefined
FF09H
Preliminary User's Manual U16315EJ1V0UD
Configuration
R
0
FF08H
0 0 0 0 0
Read the