Asynchronous Serial Interface (Uart) Mode - NEC 78K0/KD1 Series User Manual

13.4.2 Asynchronous serial interface (UART) mode

In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed.
A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of
baud rates.
(1) Register setting
The UART mode is set by asynchronous serial interface operation mode register 0 (ASIM0) and asynchronous
serial interface reception error status register 0 (ASIS0).
(a) Asynchronous serial interface operation mode register 0 (ASIM0)
This 8-bit register controls the serial transfer operations of serial interface UART0.
ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 01H.
Address: FF70H After reset: 01H R/W
Symbol 7
ASIM0 POWER0
POWER0
Note
0
1
TXE0
0
1
RXE0
0
1
Note The input from the R
Cautions 1. At startup, set POWER0 to 1 and then set TXE0 to 1. Clear TXE0 to 0 first, and then clear
POWER0 to 0.
2. At startup, set POWER0 to 1 and then set RXE0 to 1. Clear RXE0 to 0 first, and then clear
POWER0 to 0.
3. TXE0 and RXE0 are synchronized with the base clock (f
transmission unit may not be initialized if TXE0 = 1 is not set again 2 clocks after TXE0 = 0 is
set. Similarly, the reception unit may not be initialized if RXE0 = 1 is not set again 2 clocks
after RXE0 = 0 is set.
4. Be sure to set bit 0 to 1.
254
CHAPTER 13 SERIAL INTERFACE UART0
6 5
TXE0 RXE0
Enables/disables operation of internal operation clock
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit.
Enables operation of the internal operation clock.
Disables transmission (synchronously resets the transmission circuit).
Enables transmission.
Disables reception (synchronously resets the reception circuit).
Enables reception
D0 pin is fixed to high level when POWER0 = 0.
X
Preliminary User's Manual U16315EJ1V0UD
4 3
PS01 PS00 CL0
Enables/disables transmission
Enables/disables reception
XCLK
2 1 0
SL0 1
) set by BRGC0. Therefore, the