Watchdog Timer Operation When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option - NEC 78K0/KD1 Series User Manual

10.4.2 Watchdog timer operation when "Ring-OSC can be stopped by software" is selected by mask option

The operation clock of the watchdog timer can be selected as either the Ring-OSC clock or the X1 input clock.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
the watchdog timer mode register (WDTM) = 1, 1, 1) of the Ring-OSC clock.
The following shows the watchdog timer operation after reset release.
1. The status after reset release is as follows.
• Operation clock: Ring-OSC clock oscillation frequency (f
• Cycle: f 18
/2 (1.09 seconds: At operation with f
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• Counting starts
2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
Notes 1, 2, 3
instruction .
• Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4).
Ring-OSC clock (f
X1 input clock (f
XP
Watchdog timer operation stopped
• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1. As soon as WDTM is written, the counter of the watchdog timer is cleared.
2. Set bits 7, 6, and 5 to 0, 1, 1, respectively. If other values are set, the watchdog timer cannot be
operated (an error occurs in the assembler).
If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and ×, respectively, an internal
3.
reset signal is not generated even if the following processing is performed.
• WDTM is written a second time.
• A 1-bit memory manipulation instruction is executed to WDTE.
• A value other than ACH is written to WDTE.
Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.
After HALT/STOP mode is released, counting is started again using the operation clock of the
watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter
is not cleared to 0.
For the watchdog timer operation during STOP mode and HALT mode in each status, refer to 10.4.3 Watchdog
timer operation in STOP mode and 10.4.4 Watchdog timer operation in HALT mode.
CHAPTER 10 WATCHDOG TIMER
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