Uart1 Modem Status Register (U1Msr - 0Xe001 0018); User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 112: UART1 Line Status Register (U1LSR - address 0xE001 0014, read only) bit description
Bit Symbol Value Description
2 Parity Error
(PE)
0
1
3 Framing Error
(FE)
0
1
4 Break Interrupt
(BI)
0
1
5 Transmitter
Holding
Register Empty
0
(THRE)
1
6 Transmitter
Empty
(TEMT)
0
1
7 Error in RX
FIFO
(RXFE)
0
1

10.3.12 UART1 Modem Status Register (U1MSR - 0xE001 0018)

The U1MSR is a read-only register that provides status information on the modem input
signals. U1MSR[3:0] is cleared on U1MSR read. Note that modem signals have no direct
affect on UART1 operation, they facilitate software implementation of modem signal
operations.

User manual

When the parity bit of a received character is in the wrong state, a parity error
occurs. An U1LSR read clears U1LSR[2]. Time of parity error detection is
dependent on U1FCR[0].
Note: A parity error is associated with the character at the top of the UART1 RBR
FIFO.
Parity error status is inactive.
Parity error status is active.
When the stop bit of a received character is a logic 0, a framing error occurs. An
U1LSR read clears U1LSR[3]. The time of the framing error detection is dependent
on U1FCR0. Upon detection of a framing error, the RX will attempt to resynchronize
to the data and assume that the bad stop bit is actually an early start bit. However, it
cannot be assumed that the next received byte will be correct even if there is no
Framing Error.
Note: A framing error is associated with the character at the top of the UART1 RBR
FIFO.
Framing error status is inactive.
Framing error status is active.
When RXD1 is held in the spacing state (all 0's) for one full character transmission
(start, data, parity, stop), a break interrupt occurs. Once the break condition has
been detected, the receiver goes idle until RXD1 goes to marking state (all 1's). An
U1LSR read clears this status bit. The time of break detection is dependent on
U1FCR[0].
Note: The break interrupt is associated with the character at the top of the UART1
RBR FIFO.
Break interrupt status is inactive.
Break interrupt status is active.
THRE is set immediately upon detection of an empty UART1 THR and is cleared on
a U1THR write.
U1THR contains valid data.
U1THR is empty.
TEMT is set when both U1THR and U1TSR are empty; TEMT is cleared when
either the U1TSR or the U1THR contain valid data.
U1THR and/or the U1TSR contains valid data.
U1THR and the U1TSR are empty.
U1LSR[7] is set when a character with a RX error such as framing error, parity error
or break interrupt, is loaded into the U1RBR. This bit is cleared when the U1LSR
register is read and there are no subsequent errors in the UART1 FIFO.
U1RBR contains no UART1 RX errors or U1FCR[0]=0.
UART1 RBR contains at least one UART1 RX error.
Rev. 01 — 12 January 2006
UM10161
Chapter 10: UART1
Reset
value
0
0
0
1
1
0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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