Workaround; Solution 1: Test For An Irq Received During A Write To Disable Irqs - Philips LPC2101 User Manual

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This means that, on entry to the IRQ interrupt service routine, you can see the unusual
effect that an IRQ interrupt has just been taken while the I bit in the SPSR is set. In the
example above, the F bit will also be set in both the CPSR and SPSR. This means that
FIQs are disabled upon entry to the IRQ service routine, and will remain so until explicitly
re-enabled. FIQs will not be reenabled automatically by the IRQ return sequence.
Although the example shows both IRQ and FIQ interrupts being disabled, similar behavior
occurs when only one of the two interrupt types is being disabled. The fact that the core
processes the IRQ after completion of the MSR instruction which disables IRQs does not
normally cause a problem, since an interrupt arriving just one cycle earlier would be
expected to be taken. When the interrupt routine returns with an instruction like:
SUBS pc, lr, #4
the SPSR_IRQ is restored to the CPSR. The CPSR will now have the I bit and F bit set,
and therefore execution will continue with all interrupts disabled. However, this can cause
problems in the following cases:
Problem 1: A particular routine maybe called as an IRQ handler, or as a regular
subroutine. In the latter case, the system guarantees that IRQs would have been disabled
prior to the routine being called. The routine exploits this restriction to determine how it
was called (by examining the I bit of the SPSR), and returns using the appropriate
instruction. If the routine is entered due to an IRQ being received during execution of the
MSR instruction which disables IRQs, then the I bit in the SPSR will be set. The routine
would therefore assume that it could not have been entered via an IRQ.
Problem 2: FIQs and IRQs are both disabled by the same write to the CPSR. In this case,
if an IRQ is received during the CPSR write, FIQs will be disabled for the execution time of
the IRQ handler. This may not be acceptable in a system where FIQs must not be
disabled for more than a few cycles.

5.6.2 Workaround

There are 3 suggested workarounds. Which of these is most applicable will depend upon
the requirements of the particular system.

5.6.3 Solution 1: test for an IRQ received during a write to disable IRQs

Add code similar to the following at the start of the interrupt routine.
SUB
STMFD
MRS
TST
LDMNEFD sp!, {..., pc}^ ; If so, just return immediately.
User manual
•
The MSR cpsr, r0 executes to completion setting both the I bit and the F bit in the
CPSR.
•
The IRQ interrupt is taken because the core was committed to taking the interrupt
exception before the I bit was set in the CPSR.
•
The CPSR (with the I bit and F bit set) is moved to the SPSR_IRQ.
lr, lr, #4
sp!, {..., lr}
lr, SPSR
lr, #I_Bit
Rev. 01 — 12 January 2006
; Adjust LR to point to return
; Get some free regs
; See if we got an interrupt while
; interrupts were disabled.
; The interrupt will remain pending since we haven't
; acknowledged it and will be reissued when interrupts
UM10161
Chapter 5: VIC
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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