User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 177: Timer Control Register (TCR, TIMER2: T2TCR - address 0xE007 0004 and TIMER3:
Bit
0
1
7:2
16.5.3 Count Control Register (CTCR, TIMER2: T2CTCR - 0xE007 0070 and
TIMER3: T3TCR - 0xE007 4070)
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event corresponds to the one selected by bits 1:0 in the CTCR
register, the Timer Counter register will be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one half of the
PCLK clock. Consequently, duration of the HIGH/LOW levels on the same CAP input in
this case can not be shorter than 1/PCLK.
Table 178: Count Control Register (CTCR, TIMER2: T2CTCR - address 0xE007 0070 and
Bit
1:0

User manual

T3TCR - address 0xE007 4004) bit description
Symbol Description
Counter Enable When one, the Timer Counter and Prescale Counter are
enabled for counting. When zero, the counters are
disabled.
Counter Reset When one, the Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of
PCLK. The counters remain reset until TCR[1] is
returned to zero.
- Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
TIMER3: T3TCR - address 0xE007 4070) bit description
Symbol Value Description
Counter/ This field selects which rising PCLK edges can increment
Timer Timer's Prescale Counter (PC), or clear PC and increment
Mode Timer Counter (TC).
00 Timer Mode: every rising PCLK edge
01 Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
10 Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
11 Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
Rev. 01 — 12 January 2006
UM10161
Chapter 16: Timer2 and Timer3
Reset value
0
0
NA
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset
value
00
204