Fig 14. Lqfp48 Pin Configuration - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
0xE002 4080) bit description . . . . . . . . . . . . .221
Table 199:Prescaler Integer register (PREFRAC - address
0xE002 4084) bit description . . . . . . . . . . . . .221
Table 200:Prescaler cases where the Integer Counter reload
value is incremented. . . . . . . . . . . . . . . . . . . .223
Table 201:Recommended values for the RTC external
32 kHz oscillator C
Table 202:Watchdog register map. . . . . . . . . . . . . . . . . .226
Table 203:Watchdog operating modes selection. . . . . . .226
Table 204:Watchdog Mode register (WDMOD - address
0xE000 0000) bit description . . . . . . . . . . . . .227
Table 205:Watchdog Timer Constant register (WDTC -
address 0xE000 0004) bit description . . . . . .227
Table 206:Watchdog Feed register (WDFEED - address
0xE000 0008) bit description . . . . . . . . . . . . .227
Table 207:Watchdog Timer Value register (WDTV - address
0xE000 000C) bit description . . . . . . . . . . . .227
Table 208:Flash sectors in LPC2101, LPC2102,
LPC2103. . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
Table 209:ISP command summary . . . . . . . . . . . . . . . . .235
Table 210:ISP Unlock command . . . . . . . . . . . . . . . . . . .236
Table 211:ISP Set Baud Rate command. . . . . . . . . . . . .236
Table 212:Correlation between possible ISP baudrates and
external crystal frequency (in MHz) . . . . . . . .236
Table 213:ISP Echo command . . . . . . . . . . . . . . . . . . . .237
Table 214:ISP Write to RAM command. . . . . . . . . . . . . .237
Table 215:ISP Read memory command . . . . . . . . . . . . .238
Table 216:ISP Prepare sector(s) for write operation
22.5 Figures
Fig 1. LPC2101/02/03 block diagram. . . . . . . . . . . . . . . .7
Fig 2. System memory map. . . . . . . . . . . . . . . . . . . . . . .8
Fig 3. Peripheral memory map. . . . . . . . . . . . . . . . . . . . .9
Fig 4. AHB peripheral map . . . . . . . . . . . . . . . . . . . . . .10
Fig 5. Map of lower memory is showing re-mapped and
re-mappable areas (LPC2103 with 32 kB Flash) .13
Fig 6. Oscillator modes and models: a) slave mode of
operation, b) oscillation mode of operation, c)
external crystal model used for C
Fig 7. F selection algorithm . . . . . . . . . . . . . . . . . . .18
OSC
Fig 8. External interrupt logic . . . . . . . . . . . . . . . . . . . . .22
Fig 9. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . .26
Fig 10. Reset block diagram including the wake-up timer 35
Fig 11. APB divider connections . . . . . . . . . . . . . . . . . . .37
Fig 12. Simplified block diagram of the Memory Accelerator
Module (MAM) . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Fig 13. Block diagram of the Vectored Interrupt Controller
(VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Fig 14. LQFP48 pin configuration . . . . . . . . . . . . . . . . . .60

User manual
components . . . . . . .224
X1/X2
/ evaluation17
X1 X2
Rev. 01 — 12 January 2006
Chapter 22: Supplementary information
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 217:ISP Copy command . . . . . . . . . . . . . . . . . . . . 239
Table 218:ISP Go command. . . . . . . . . . . . . . . . . . . . . . 239
Table 219:ISP Erase sector command . . . . . . . . . . . . . . 240
Table 220:ISP Blank check sector command . . . . . . . . . 240
Table 221:ISP Read part identification number
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 222:LPC2101/02/03 part identification numbers. . 240
Table 223:ISP Read Boot code version number
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 224:ISP Compare command. . . . . . . . . . . . . . . . . 241
Table 225:ISP Return codes Summary . . . . . . . . . . . . . 241
Table 226:IAP command summary. . . . . . . . . . . . . . . . . 244
Table 227:IAP Prepare sector(s) for write
operation command . . . . . . . . . . . . . . . . . . . . 244
Table 228:IAP Copy RAM to flash command . . . . . . . . . 245
Table 229:IAP Erase sector(s) command . . . . . . . . . . . . 246
Table 230:IAP Blank check sector(s) command . . . . . . . 246
Table 231:IAP Read Part Identification command . . . . . 246
Table 232:IAP Read Boot code version number
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 233:IAP Compare command. . . . . . . . . . . . . . . . . 247
Table 234:Reinvoke ISP . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 235:IAP status codes summary . . . . . . . . . . . . . . 248
Table 236:EmbeddedICE pin description . . . . . . . . . . . . 250
Table 237:EmbeddedICE logic registers . . . . . . . . . . . . 251
Table 238:RealMonitor stack requirement . . . . . . . . . . . 257
Table 239:Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 265
Fig 15. PLCC44 pin configuration . . . . . . . . . . . . . . . . . . 61
Fig 16. Illustration of the fast and slow GPIO access and
output showing 3.5 x increase of the pin output
frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Fig 17. Autobaud a) mode 0 and b) mode 1 waveform. . 96
Fig 18. UART0 block diagram . . . . . . . . . . . . . . . . . . . . . 98
Fig 19. Auto-RTS functional timing . . . . . . . . . . . . . . . . 110
Fig 20. Auto-CTS functional timing . . . . . . . . . . . . . . . . 111
Fig 21. Autobaud a) mode 0 and b) mode 1 waveform 116
Fig 22. UART1 block diagram . . . . . . . . . . . . . . . . . . . . 118
2
Fig 23. I C-bus configuration. . . . . . . . . . . . . . . . . . . . . 120
Fig 24. Format in the Master Transmitter mode . . . . . . 121
Fig 25. Format of Master Receiver mode . . . . . . . . . . . 122
Fig 26. A Master Receiver switches to Master Transmitter
after sending repeated START . . . . . . . . . . . . . 122
Fig 27. Format of Slave Receiver mode . . . . . . . . . . . . 123
Fig 28. Format of Slave Transmitter mode . . . . . . . . . . 123
2
Fig 29. I C serial interface block diagram . . . . . . . . . . . 124
Fig 30. Arbitration procedure. . . . . . . . . . . . . . . . . . . . . 125
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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