Architecture; User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
PCLK
prescale
counter
timer
counter
timer counter
reset
interrupt
Fig 50. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled
PCLK
prescale counter
timer counter
TCR[0]
(counter enable)
interrupt
Fig 51. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled

15.7 Architecture

The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in
Figure

User manual

2 0 1 2
4 5
2 0 1 2
4 5
1
52.
Rev. 01 — 12 January 2006
0 1 2 0
6
0
6
0
UM10161
Chapter 15: Timer0 and Timer1
1 2 0 1
0 1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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