NEC UPD703116 User Manual page 774

32-bit single-chip microcontrollers
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(4) Multiplex bus timing
(a) CLKOUT asynchronous (T
Parameter
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
Address float delay time from RD↓
Data input setup time from address
Data input setup time from RD ↓
Delay time from ASTB↓ to RD, LWR, UWR↓
Data input hold time (from RD↑)
Address output time from RD↑
Delay time from RD, LWR, UWR ↑ to ASTB↑
Delay time from RD↑ to ASTB↓
RD, LWR, UWR low-level width
ASTB high-level width
Data output time from LWR, UWR↓
Data output setup time (to LWR, UWR↑)
Data output hold time (from LWR, UWR↑)
WAIT setup time (to address)
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
HLDRQ high-level width
HLDAK low-level width
Delay time from address float to HLDAK↓
Delay time from HLDAK↑ to bus output
Delay time from HLDRQ↓ to HLDAK↓
Delay time from HLDRQ↑ to HLDAK↑
774
CHAPTER 18 ELECTRICAL SPECIFICATIONS
µ
= –40 to +85°C:
PD703116, 703116(A), 70F3116, 70F3116(A),
A
µ
= –40 to +110°C:
T
PD703116(A1), 70F3116(A1),
A
V
= CV
= 3.0 to 3.6 V, V
DD3
DD
output pin load capacitance: C
Symbol
<16>
t
SAST
<17>
t
HSTA
<18>
t
FRDA
<19>
t
SAID
<20>
t
SRDID
<21>
t
DSTRDWR
<22>
t
HRDID
<23>
t
DRDA
<24>
t
DRDWRST
<25>
t
DRDST
<26>
t
WRDWRL
<27>
t
WSTH
<28>
t
DWROD
<29>
t
SODWR
<30>
t
HWROD
<31>
t
SAWT1
<32>
t
SAWT2
<33>
t
HAWT1
<34>
t
HAWT2
<35>
t
SSTWT1
<36>
t
SSTWT2
<37>
t
HSTWT1
<38>
t
HSTWT2
<39>
t
WHQH
<40>
t
WHAL
<41>
t
DFHA
<42>
t
DHAC
<43>
t
DHQHA1
<44>
t
DHQHA2
User's Manual U14492EJ5V0UD
= 5 V ±0.5 V, V
= V
DD5
SS3
= 50 pF)
L
Conditions
MIN.
(0.5 + w
)T – 16
AS
(0.5 + w
)T – 15
AH
(0.5 + w
)T – 15
AH
0
(1 + i)T – 15
0.5T – 15
(1.5 + i + w
)T
AS
– 15
(1 + w)T – 22
(1 + w
)T – 15
AS
(1 + w)T – 25
T – 20
w ≥ 1
w ≥ 1
(0.5 + w + w
+ w
AS
AH
(1.5 + w + w
+ w
AS
AH
w ≥ 1
w ≥ 1
(w + w
)T
AH
(1 + w + w
)T
AH
T + 10
T – 15
–12
–7
2T
0.5T
= CV
= 0 V,
SS5
SS
MAX.
Unit
ns
ns
11
ns
(2 + w + w
+ w
)T
ns
AS
AH
– 40
(1 + w)T – 40
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
ns
ns
(1.5 + w
+ w
)T
ns
AS
AH
– 40
(1.5 + w + w
+ w
)T
ns
AS
AH
– 40
)T
ns
)T
ns
(1 + w
)T – 32
ns
AH
(1 + w + w
)T
ns
AH
– 32
ns
ns
ns
ns
ns
ns
ns
1.5T + 30
ns

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