Interrupt Factors - NEC UPD703116 User Manual

(7) Read values of DSAn and DDAn registers
If the values of the DSAn and DDAn registers are read during DMA transfer, the values in the middle of being
updated may be read (n = 0 to 3).
For example, if the DSAnH register and the DSAnL register are read in that order when the value of the DMA
transfer source address (DSAn register) is "0000FFFFH" and the counting direction is incremental (when the
SADn1 and SADn0 bits of the DADCn register = 00), the value of the DSAnL register differs as follows
depending on whether DMA transfer is executed immediately after the DSAnH register has been read.
(a) If DMA transfer does not occur while the DSAn register is being read
<1> Reading DSAnH register: DSAnH = 0000H
<2> Reading DSAnL register: DSAnL = FFFFH
(b) If DMA transfer occurs while the DSAn register is being read
<1> Reading DSAnH register: DSAnH = 0000H
<2> Occurrence of DMA transfer
<3> Incrementing DSAn register : DSAn = 00010000H
<4> Reading DSAnL register: DSAnL = 0000H

6.14.1 Interrupt factors

DMA transfer is interrupted if a bus hold is issued.
If the factor (bus hold) interrupting DMA transfer disappears, DMA transfer promptly restarts.
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
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