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The CPU of the V850E/IA1 is based on RISC architecture and executes almost all instructions in one clock cycle,
using 5-stage pipeline control.
3.1 Features
• Minimum instruction execution time: 20 ns (@ internal 50 MHz operation)
• Memory space
Program space: 64 MB linear
Data space:
• Thirty-two 32-bit general-purpose registers
• Internal 32-bit architecture
• Five-stage pipeline control
• Multiplication/division instructions
• Saturated operation instructions
• One-clock 32-bit shift instruction
• Long/short format load/store instructions
• Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
48
CHAPTER 3 CPU FUNCTION
4 GB linear
User's Manual U14492EJ5V0UD
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