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(9) Timer 2 sub-channel 3, 4 capture/compare control register (CMSE340)
The CMSE340 register controls the timer 2 sub-channel n sub capture/compare register (CVSEn0) and the
timer 2 sub-channel n main capture/compare register (CVPEn0) (n = 3, 4).
This register can be read/written in 16-bit units.
15
14
13
CMSE340
0
0
EEVE4
Bit position
Bit name
13, 5
EEVEn
12, 4
BFEEn
Remark
n = 3, 4
346
CHAPTER 9 TIMER/COUNTER FUNCTION
12
11
10
9
8
7
BFEE4
LNKE4
CCSE4
TB1E4
TB0E4
0
Enables/disables event detection by CMSE340 register.
0: ED1 and ED2 signal inputs ignored (nothing is done even if these signals are
input).
1: Operation caused by ED1 and ED2 signal inputs enabled.
Specifies the sub-channel n sub capture/compare register (CVSEn0) buffer
operation.
0: Don't use sub-channel n sub capture/compare register (CVSEn0) as buffer.
1: Use sub-channel n sub capture/compare register (CVSEn0) as buffer.
Caution When the BFEEn bit = 1, a compare match occurs on starting the
timer in the compare register mode because the values of both the
TM2x and CVPEn0 registers are 0 after reset (TM2x = timer/counter
selected by TB1En and TB0En bits, n = 1 to 4). After that, the value
of the sub register (CVSEn0) is written to the main register (CVPEn0).
Remarks 1. The operations in the capture register mode and compare register
mode when the sub-channel n sub capture/compare register (CVSEn0)
is not used as a buffer are shown below.
• In capture register mode: The CPU can read both the master register
(CVPEn0) and slave register (CVSEn0). The next event is ignored
until the CPU finishes reading the master register.
TM20 capture is performed by the slave register, and TM21 capture
is performed by the master register.
• In compare register mode: The CPU writes to the slave register
(CVSEn0), and immediately after, the same contents as those of the
slave register are written to the master register (CVPEn0).
2. The operations in the capture register mode and compare register
mode when the sub-channel n sub capture/compare register (CVSEn0)
is used as a buffer are shown below.
• In capture register mode: When the CPU reads the master register
(CVPEn0), the master register updates the value held by the slave
register (CVSEn0) immediately before the CPU read operation.
When a capture event occurs, the timer/counter value at that time is
always saved in the slave register.
• In compare register mode: The CPU writes to the slave register
(CVSEn0) and these contents are transferred to the master register
(CVPEn0) set with the LNKEn bits.
User's Manual U14492EJ5V0UD
6
5
4
3
2
1
0
EEVE3
BFEE3
LNKE3
CCSE3
TB1E3
Function
0
Address
Initial value
TB0E3
FFFFF64EH
0000H
(1/2)
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