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Figure 9-33. Change Timing from 100% Duty State (PWM Mode 2)
count value
BFCM0nx
Interrupt request
Positive phase
(TO0n0, TO0n2, TO0n4)
Negative phase
(TO0n1, TO0n3, TO0n5)
Note F/F is reset upon occurrence of match with CM0nx.
Remarks 1. n = 0, 1
2. x = 0 to 2
3. b > CM0n3
4. t: Dead time = (DTRRn + 1)/f
5. The above figure shows an active high case.
The timing at which the F/F is reset is upon occurrence of match with CM0nx as normal.
278
CHAPTER 9 TIMER/COUNTER FUNCTION
CM0n3
TM0n
a
0000H
CM0nx
match
a
b
a
CM0nx
INTCM0n3
F/F
DTMnx
t
t
(f
CLK
CLK
User's Manual U14492EJ5V0UD
CM0n3
b
c
b
b
INTCM0n3
INTCM0n3
t
: Base clock)
CM0n3
CM0n3
c
CM0nx
match
d
c
INTCM0n3
Note
t
t
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