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8.6 Securing Oscillation Stabilization Time
8.6.1 Oscillation stabilization time security specification
Two specification methods can be used to secure the time from when software STOP mode is released until the
stopped oscillator stabilizes.
(1) Securing the time using an on-chip time base counter
Software STOP mode is released when a valid edge is input to the NMI pin or a maskable interrupt request is
input (INTPn). When a valid edge is input to the pin causing the start of oscillation, the time base counter
(TBC) starts counting, and the time until the clock output from the oscillator stabilizes is secured during that
counting time (n = 0 to 6, 20 to 25).
Oscillation stabilization time = TBC counting time
After a fixed time, internal system clock output begins, and processing branches to the NMI interrupt or
maskable interrupt (INTPn) handler address.
Oscillation waveform (X2)
Internal main clock
CLKOUT (output)
STOP state
Note
NMI (input)
Note Valid edge: When specified as the rising edge.
The NMI pin should usually be set to an inactive level (for example, high level when the valid edge is
specified as the falling edge) in advance.
Software STOP mode is immediately released if an operation is performed according to NMI valid edge input
or maskable interrupt request input (INTPn) timing in which software STOP mode is set until the CPU
acknowledges the interrupt.
If direct mode or external clock connection mode (CESEL bit of CKC register = 1) is used, program execution
begins after the count time of the time base counter has elapsed.
Also, even if PLL mode and resonator connection mode (CESEL bit of CKC register = 0) are used, program
execution begins after the oscillation stabilization time is secured according to the time base counter.
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CHAPTER 8 CLOCK GENERATION FUNCTION
Set software STOP mode
Oscillator is stopped
User's Manual U14492EJ5V0UD
Time base counter's
counting time
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