Dma Addressing Control Registers 0 To 3 (Dadc0 To Dadc3) - NEC UPD703116 User Manual

32-bit single-chip microcontrollers

Table of Contents

6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3)

These 16-bit registers are used to control the DMA transfer modes for DMA channel n (n = 0 to 3). These registers

cannot be accessed during DMA operation.

These registers can be read/written in 16-bit units.

Be sure to set bits 0, 1, and 8 to 13 to 0. If they are set to 1, the operation is not guaranteed.

Cautions 1. The DS1 and DS0 bits are used to set how many bits of data are transferred.

When 8-bit data (DS1, DS0 bits = 00) is set, the lower data bus (AD0 to AD7) is not necessarily

When the transfer data size is set to 16 bits, the transfer must start from an address with bit 1

of the lower address aligned to "0". In this case, the transfer cannot start from an odd

2. Set the DADCn register when the corresponding channel is in one of the following periods

(the operation is not guaranteed if set at another timing).

• Time from system reset to generation of the first DMA transfer request

• Time from DMA transfer end (after terminal count) to generation of the next DMA transfer

• Time from the forcible termination of DMA transfer (after the INITn bit of DMA channel

control register n (DCHCn) has been set to 1) to generation of the next DMA transfer

Bit position

CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)

0 SAD1 SAD0 DAD1 DAD0 TM1 TM0

Sets the transfer data size for DMA transfer.

Setting prohibited

For the on-chip peripheral I/O and programmable peripheral I/O registers, ensure the

transfer size matches the access size.

User's Manual U14492EJ5V0UD

Transfer data size

Initial value