Hitachi SH7750 Hardware Manual page 64

Table 1.2 Pin Functions (cont)
Pin
No. No. Pin Name
29 K2 D42
30 K1 D37
31 K3 VDDQ
32 K4 VSSQ
33 L1 D41
34 L2 D38
35 M1 D40
36 M2 D39
37 L3 VDDQ
38 L4 VSSQ
39 N1 D15
40 N2 D0
41 P1 D14
42 P2 D1
43 M3 VDDQ
44 M4 VSSQ
45 R1 D13
46 R2 D2
47 P3 VDD
48 P4 VSS
49 T1 D12
50 T2 D3
51 R3 VDDQ
52 R4 VSSQ
53 U1 D11
54 U2 D4
55 V1 D10
56 V2 D5
57 T3 VDDQ
58 T4 VSSQ
59 W1 D9
60 Y1 D6
Rev. 6.0, 07/02, page 14 of 986
I/O Function
I/O Data/port
I/O Data/port
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O Data/port
I/O Data/port
I/O Data/port
I/O Data/port
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O Data
I/O Data
I/O Data
I/O Data
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O Data
I/O Data
Power Internal VDD
Power Internal GND
(0 V)
I/O Data
I/O Data
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O Data
I/O Data
I/O Data
I/O Data
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O Data
I/O Data
Reset SRAM DRAM
(Port) (Port)
(Port) (Port)
(Port) (Port)
(Port) (Port)
(Port) (Port)
(Port) (Port)
Memory Interface
SDRAM PCMCIA MPX
(Port) (Port) (Port)
(Port) (Port) (Port)
(Port) (Port) (Port)
(Port) (Port) (Port)
(Port) (Port) (Port)
(Port) (Port) (Port)
A15
A0
A14
A1
A13
A2
A12
A3
A11
A4
A10
A5
A9
A6