Interrupt-Priority-Level Setting Register 00 (Intpri00) (Sh7750R Only) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

Hide thumbs Also See for SH7750:

Table of Contents

Bit 7—IRL Pin Mode (IRLM): Specifies whether pins IRL3–IRL0 are to be used as level-

encoded interrupt requests or as four independent interrupt requests.

Bits 13 to 10 and 6 to 0—Reserved: These bits are always read as 0, and should only be written

Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)

The interrupt-priority-level setting register 00 (INTPRI00) sets the priority levels (levels 15–0) for

the on-chip peripheral module interrupts. INTPRI00 is a 32-bit readable/writable register. It is

initialized to H'00000000 by a reset, but is not initialized when the device enters standby mode.

Initial value:

Initial value:

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Table 19.7 shows the correspondence between interrupt request sources and the bits in INTPRI00.

Rev. 6.0, 07/02, page 764 of 986

IRL pins used as level-encoded interrupt requests

IRL pins used as four independent interrupt requests (level-sense IRQ

(Initial value)

Table of Contents

Sh7750r Sh7750s