Table 13.3 External Memory Space Map - Hitachi SH7750 Hardware Manual

Table 13.3 External Memory Space Map

External
Area Addresses
0 H'00000000–
H'03FFFFFF
1 H'04000000–
H'07FFFFFF
2 H'08000000–
H'0BFFFFFF
3 H'0C000000–
H'0FFFFFFF
4 H'10000000–
H'13FFFFFF
5 H'14000000–
H'17FFFFFF
6 H'18000000–
H'1BFFFFFF
5
7 *
H'1C000000–
H'1FFFFFFF
Notes: *1 Memory bus width specified by external pins
*2 Memory bus width specified by register
*3 With synchronous DRAM interface, bus width is 32 or 64 bits only.
With DRAM interface, bus width is 16 or 32 bits only for area 2, and 16, 32, or 64 bits
only for area 3. Bus width of area 2 is as same as that of area 3 which is specified by
MCR.
*4 With PCMCIA interface, bus width is 8 or 16 bits only.
*5 Do not access a reserved area, as operation cannot be guaranteed in this case.
*6 64-bit access applies only to transfer by the DMAC. (CHCRn. TS = 000)
In a transfer to an external memory by FMOV (FPSCR.SZ = 1), two transfer operations,
each with an access size of 32 bits, are conducted.
*7 Settable only for SH7750R.
Rev. 6.0, 07/02, page 320 of 986
Connectable
Size Memory
64 Mbytes SRAM
Burst ROM
MPX
64 Mbytes SRAM
MPX
Byte control SRAM
64 Mbytes SRAM
Synchronous DRAM 32, 64 *
DRAM
MPX
64 Mbytes SRAM
Synchronous DRAM 32, 64 *
DRAM
MPX
64 Mbytes SRAM
MPX
Byte control RAM
64 Mbytes SRAM
MPX
Burst ROM
PCMCIA
64 Mbytes SRAM
MPX
Burst ROM
PCMCIA
64 Mbytes —
Settable Bus
Widths Access Size
1
8, 16, 32, 64 *
8, 16, 32,
64 *
1 7
8, 16, 32 * , 64 *
32 bytes
1
32, 64 *
2
8, 16, 32, 64 *
8, 16, 32,
64 *
2
32, 64 *
32 bytes
2
16, 32, 64 *
2
8, 16, 32, 64 *
8, 16, 32,
64 *
2 3
*
32 bytes
2 3
16, 32 * *
2
32, 64 *
2
8, 16, 32, 64 *
8, 16, 32,
64 *
2 3
*
32 bytes
2 3
16, 32, 64 * *
2
32, 64 *
2
8, 16, 32, 64 *
8, 16, 32,
64 *
2
32, 64 *
32 bytes
2
16, 32, 64 *
2
8, 16, 32, 64 *
8, 16, 32,
64 *
2
32, 64 *
32 bytes
2 7
8, 16, 32 * , 64 *
2 4
8, 16 * *
2
8, 16, 32, 64 *
8, 16, 32,
64 *
2
32, 64 *
32 bytes
2 7
8,16, 32 * , 64 *
2 4
8,16 * *
—
6
bits,
6
bits,
6
bits,
6
bits,
6
bits,
6
bits,
6
bits,