Hitachi SH7750 Hardware Manual page 312

Sh7750 series superh risc engine

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Bit 4—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed in

watchdog timer mode. This flag is not set in interval timer mode.

Bit 3—Interval Timer Overflow Flag (IOVF): Indicates that WTCNT has overflowed in

interval timer mode. This flag is not set in watchdog timer mode.

Bits 2 to 0—Clock Select 2 to 0 (CKS2–CKS0): These bits select the clock used for the WTCNT

count from eight clocks obtained by dividing the frequency divider 2 input clock*. The overflow

periods shown in the following table are for use of a 33 MHz input clock, with frequency divider 1

off, and PLL circuit 1 on (×6).

Note: * When PLL1 is switched on or off, the clock following the switch is used.

Note: The up-count may not be performed correctly if bits CKS2–CKS0 are modified while the

WDT is running. Always stop the WDT before modifying these bits.

Rev. 6.0, 07/02, page 262 of 986

WTCNT has overflowed in watchdog timer mode

WTCNT has overflowed in interval timer mode

Clock Division Ratio

(Initial value)

(Initial value)

Overflow Period

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