Figure 3.4 P4 Area - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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P4 Area: The P4 area is mapped onto SH7750 Series on-chip I/O channels. This area cannot be

accessed using the cache. The P4 area is shown in detail in figure 3.4.

The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues

(SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the

MMUCR.SQMD bit. For details, see section 4.7, Store Queues.

The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache

address array. For details, see section 4.5.1, IC Address Array.

The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data

array. For details, see section 4.5.2, IC Data Array.

The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB

address array. For details, see section 3.7.1, ITLB Address Array.

Rev. 6.0, 07/02, page 66 of 986

Instruction cache address array

Instruction TLB address array

Instruction TLB data arrays 1 and 2

Operand cache address array

Unified TLB data arrays 1 and 2

Figure 3.4 P4 Area

Reserved area

Instruction cache data array

Operand cache data array

Unified TLB address array

Reserved area

Control register area

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