Figure 22.20 Burst Rom Bus Cycle (1St Data: One Internal Wait + One External Wait; 2Nd/3Rd/4Th Data: One Internal Wait) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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Figure 22.20 Burst ROM Bus Cycle

(1st Data: One Internal Wait + One External Wait; 2nd/3rd/4th Data: One Internal Wait)

Rev. 6.0, 07/02, page 882 of 986

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